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git01.mediatek.com / filogic / atf / fa3cf0bf903ad0d8320713870ca58410e1ab8758 / . / bl1 / aarch64 / bl1_entrypoint.S
blob: 36ce0d0b47c786cec00a374e6825b0e7ee662c3d [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]1/*
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100[diff] [blame]2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame^]4 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]5 */
6
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000[diff] [blame]7#include <arch.h>
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100[diff] [blame]8#include <el3_common_macros.S>
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]9
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +0000[diff] [blame]10 .globl bl1_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]11
12
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]13 /* -----------------------------------------------------
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +0000[diff] [blame]14 * bl1_entrypoint() is the entry point into the trusted
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]15 * firmware code when a cpu is released from warm or
16 * cold reset.
17 * -----------------------------------------------------
18 */
19
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]20func bl1_entrypoint
Sandrine Bailleux449dbd52015-06-02 17:19:43 +0100[diff] [blame]21 /* ---------------------------------------------------------------------
22 * If the reset address is programmable then bl1_entrypoint() is
23 * executed only on the cold boot path. Therefore, we can skip the warm
24 * boot mailbox mechanism.
25 * ---------------------------------------------------------------------
26 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100[diff] [blame]27 el3_entrypoint_common \
28 _set_endian=1 \
Sandrine Bailleux449dbd52015-06-02 17:19:43 +0100[diff] [blame]29 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
Sandrine Bailleuxb21b02f2015-10-30 15:05:17 +0000[diff] [blame]30 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100[diff] [blame]31 _init_memory=1 \
32 _init_c_runtime=1 \
33 _exception_vectors=bl1_exceptions
Vikram Kanigiri96377452014-04-24 11:02:16 +0100[diff] [blame]34
35 /* ---------------------------------------------
36 * Architectural init. can be generic e.g.
37 * enabling stack alignment and platform spec-
38 * ific e.g. MMU & page table setup as per the
39 * platform memory map. Perform the latter here
40 * and the former in bl1_main.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]41 * ---------------------------------------------
42 */
Vikram Kanigiri96377452014-04-24 11:02:16 +0100[diff] [blame]43 bl bl1_early_platform_setup
44 bl bl1_plat_arch_setup
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]45
Vikram Kanigiri96377452014-04-24 11:02:16 +0100[diff] [blame]46 /* --------------------------------------------------
47 * Initialize platform and jump to our c-entry point
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100[diff] [blame]48 * for this type of reset.
Vikram Kanigiri96377452014-04-24 11:02:16 +0100[diff] [blame]49 * --------------------------------------------------
50 */
51 bl bl1_main
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100[diff] [blame]52
53 /* --------------------------------------------------
54 * Do the transition to next boot image.
55 * --------------------------------------------------
56 */
57 b el3_exit
Kévin Petita877c252015-03-24 14:03:57 +0000[diff] [blame]58endfunc bl1_entrypoint