| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
| Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 31 | #include <arch.h> |
| Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 32 | #include <el3_common_macros.S> |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 33 | |
| Jeenu Viswambharan | 2a30a75 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 34 | .globl bl1_entrypoint |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 35 | |
| 36 | |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 37 | /* ----------------------------------------------------- |
| Jeenu Viswambharan | 2a30a75 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 38 | * bl1_entrypoint() is the entry point into the trusted |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 39 | * firmware code when a cpu is released from warm or |
| 40 | * cold reset. |
| 41 | * ----------------------------------------------------- |
| 42 | */ |
| 43 | |
| Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 44 | func bl1_entrypoint |
| Sandrine Bailleux | 449dbd5 | 2015-06-02 17:19:43 +0100 | [diff] [blame] | 45 | /* --------------------------------------------------------------------- |
| 46 | * If the reset address is programmable then bl1_entrypoint() is |
| 47 | * executed only on the cold boot path. Therefore, we can skip the warm |
| 48 | * boot mailbox mechanism. |
| 49 | * --------------------------------------------------------------------- |
| 50 | */ |
| Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 51 | el3_entrypoint_common \ |
| 52 | _set_endian=1 \ |
| Sandrine Bailleux | 449dbd5 | 2015-06-02 17:19:43 +0100 | [diff] [blame] | 53 | _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ |
| Sandrine Bailleux | b21b02f | 2015-10-30 15:05:17 +0000 | [diff] [blame^] | 54 | _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ |
| Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 55 | _init_memory=1 \ |
| 56 | _init_c_runtime=1 \ |
| 57 | _exception_vectors=bl1_exceptions |
| Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 58 | |
| 59 | /* --------------------------------------------- |
| 60 | * Architectural init. can be generic e.g. |
| 61 | * enabling stack alignment and platform spec- |
| 62 | * ific e.g. MMU & page table setup as per the |
| 63 | * platform memory map. Perform the latter here |
| 64 | * and the former in bl1_main. |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 65 | * --------------------------------------------- |
| 66 | */ |
| Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 67 | bl bl1_early_platform_setup |
| 68 | bl bl1_plat_arch_setup |
| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 69 | |
| Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 70 | /* -------------------------------------------------- |
| 71 | * Initialize platform and jump to our c-entry point |
| 72 | * for this type of reset. Panic if it returns |
| 73 | * -------------------------------------------------- |
| 74 | */ |
| 75 | bl bl1_main |
| 76 | panic: |
| 77 | b panic |
| Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 78 | endfunc bl1_entrypoint |