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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Manish V Badarkheeba13bd2022-01-08 23:08:02 +00002 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
9#include <platform_def.h>
10
Dan Handley9df48042015-03-19 18:58:55 +000011#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <bl1/bl1.h>
13#include <common/bl_common.h>
Louis Mayencourt5a15b2d2019-10-17 14:46:51 +010014#include <lib/fconf/fconf.h>
Manish V Badarkhe99a8e142020-06-11 22:32:11 +010015#include <lib/fconf/fconf_dyn_cfg_getter.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <lib/utils.h>
17#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000018#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <plat/common/platform.h>
20
Dan Handley9df48042015-03-19 18:58:55 +000021/* Weak definitions may be overridden in specific ARM standard platform */
22#pragma weak bl1_early_platform_setup
23#pragma weak bl1_plat_arch_setup
Dan Handley9df48042015-03-19 18:58:55 +000024#pragma weak bl1_plat_sec_mem_layout
Gary Morrison3d7f6542021-01-27 13:08:47 -060025#pragma weak arm_bl1_early_platform_setup
Yatharth Kocharede39cb2016-11-14 12:01:04 +000026#pragma weak bl1_plat_prepare_exit
Sathees Balya22576072018-09-03 17:41:13 +010027#pragma weak bl1_plat_get_next_image_id
28#pragma weak plat_arm_bl1_fwu_needed
Gary Morrison3d7f6542021-01-27 13:08:47 -060029#pragma weak arm_bl1_plat_arch_setup
laurenw-arm56f1e3e2021-03-03 14:19:38 -060030#pragma weak arm_bl1_platform_setup
Dan Handley9df48042015-03-19 18:58:55 +000031
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010032#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
33 bl1_tzram_layout.total_base, \
34 bl1_tzram_layout.total_size, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050035 MT_MEMORY | MT_RW | EL3_PAS)
Daniel Boulby4e97abd2018-07-16 14:09:15 +010036/*
37 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
38 * otherwise one region is defined containing both
39 */
40#if SEPARATE_CODE_AND_RODATA
41#define MAP_BL1_RO MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010042 BL_CODE_BASE, \
43 BL1_CODE_END - BL_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050044 MT_CODE | EL3_PAS), \
Daniel Boulby4e97abd2018-07-16 14:09:15 +010045 MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010046 BL1_RO_DATA_BASE, \
47 BL1_RO_DATA_END \
48 - BL_RO_DATA_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050049 MT_RO_DATA | EL3_PAS)
Daniel Boulby4e97abd2018-07-16 14:09:15 +010050#else
51#define MAP_BL1_RO MAP_REGION_FLAT( \
52 BL_CODE_BASE, \
53 BL1_CODE_END - BL_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050054 MT_CODE | EL3_PAS)
Daniel Boulby4e97abd2018-07-16 14:09:15 +010055#endif
Dan Handley9df48042015-03-19 18:58:55 +000056
57/* Data structure which holds the extents of the trusted SRAM for BL1*/
58static meminfo_t bl1_tzram_layout;
59
Manish V Badarkhebc4350b2020-07-14 11:28:36 +010060/* Boolean variable to hold condition whether firmware update needed or not */
61static bool is_fwu_needed;
62
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020063struct meminfo *bl1_plat_sec_mem_layout(void)
Dan Handley9df48042015-03-19 18:58:55 +000064{
65 return &bl1_tzram_layout;
66}
67
68/*******************************************************************************
69 * BL1 specific platform actions shared between ARM standard platforms.
70 ******************************************************************************/
71void arm_bl1_early_platform_setup(void)
72{
Dan Handley9df48042015-03-19 18:58:55 +000073
Juan Castillob6132f12015-10-06 14:01:35 +010074#if !ARM_DISABLE_TRUSTED_WDOG
75 /* Enable watchdog */
Aditya Angadi20b48412019-04-16 11:29:14 +053076 plat_arm_secure_wdt_start();
Juan Castillob6132f12015-10-06 14:01:35 +010077#endif
78
Dan Handley9df48042015-03-19 18:58:55 +000079 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010080 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000081
82 /* Allow BL1 to see the whole Trusted RAM */
83 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
84 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
Dan Handley9df48042015-03-19 18:58:55 +000085}
86
87void bl1_early_platform_setup(void)
88{
89 arm_bl1_early_platform_setup();
90
91 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000092 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +000093 * No need for locks as no other CPU is active.
94 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000095 plat_arm_interconnect_init();
Dan Handley9df48042015-03-19 18:58:55 +000096 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000097 * Enable Interconnect coherency for the primary CPU's cluster.
Dan Handley9df48042015-03-19 18:58:55 +000098 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000099 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000100}
101
102/******************************************************************************
103 * Perform the very early platform specific architecture setup shared between
104 * ARM standard platforms. This only does basic initialization. Later
105 * architectural setup (bl1_arch_setup()) does not do anything platform
106 * specific.
107 *****************************************************************************/
108void arm_bl1_plat_arch_setup(void)
109{
Soby Mathewb9856482018-09-18 11:42:42 +0100110#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
111 /*
112 * Ensure ARM platforms don't use coherent memory in BL1 unless
113 * cryptocell integration is enabled.
114 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100115 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000116#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100117
118 const mmap_region_t bl_regions[] = {
119 MAP_BL1_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100120 MAP_BL1_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100121#if USE_ROMLIB
122 ARM_MAP_ROMLIB_CODE,
123 ARM_MAP_ROMLIB_DATA,
Soby Mathewb9856482018-09-18 11:42:42 +0100124#endif
125#if ARM_CRYPTOCELL_INTEG
126 ARM_MAP_BL_COHERENT_RAM,
127#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100128 {0}
129 };
130
Roberto Vargas344ff022018-10-19 16:44:18 +0100131 setup_page_tables(bl_regions, plat_arm_get_mmap());
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700132#ifdef __aarch64__
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100133 enable_mmu_el3(0);
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700134#else
135 enable_mmu_svc_mon(0);
136#endif /* __aarch64__ */
Roberto Vargase3adc372018-05-23 09:27:06 +0100137
138 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000139}
140
141void bl1_plat_arch_setup(void)
142{
143 arm_bl1_plat_arch_setup();
144}
145
146/*
147 * Perform the platform specific architecture setup shared between
148 * ARM standard platforms.
149 */
150void arm_bl1_platform_setup(void)
151{
Manish V Badarkhe99a8e142020-06-11 22:32:11 +0100152 const struct dyn_cfg_dtb_info_t *fw_config_info;
153 image_desc_t *desc;
154 uint32_t fw_config_max_size;
155 int err = -1;
156
Dan Handley9df48042015-03-19 18:58:55 +0000157 /* Initialise the IO layer and register platform IO devices */
158 plat_arm_io_setup();
Louis Mayencourt5a15b2d2019-10-17 14:46:51 +0100159
Manish V Badarkhe99a8e142020-06-11 22:32:11 +0100160 /* Check if we need FWU before further processing */
Manish V Badarkhebc4350b2020-07-14 11:28:36 +0100161 is_fwu_needed = plat_arm_bl1_fwu_needed();
162 if (is_fwu_needed) {
Manish V Badarkhe99a8e142020-06-11 22:32:11 +0100163 ERROR("Skip platform setup as FWU detected\n");
164 return;
165 }
166
167 /* Set global DTB info for fixed fw_config information */
168 fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
Manish V Badarkhefc0b8672022-04-21 22:53:43 +0100169 set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID);
Manish V Badarkhe99a8e142020-06-11 22:32:11 +0100170
171 /* Fill the device tree information struct with the info from the config dtb */
172 err = fconf_load_config(FW_CONFIG_ID);
173 if (err < 0) {
174 ERROR("Loading of FW_CONFIG failed %d\n", err);
175 plat_error_handler(err);
176 }
177
178 /*
179 * FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing
180 * is successful then load TB_FW_CONFIG device tree.
181 */
182 fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
183 if (fw_config_info != NULL) {
184 err = fconf_populate_dtb_registry(fw_config_info->config_addr);
185 if (err < 0) {
186 ERROR("Parsing of FW_CONFIG failed %d\n", err);
187 plat_error_handler(err);
188 }
189 /* load TB_FW_CONFIG */
190 err = fconf_load_config(TB_FW_CONFIG_ID);
191 if (err < 0) {
192 ERROR("Loading of TB_FW_CONFIG failed %d\n", err);
193 plat_error_handler(err);
194 }
195 } else {
196 ERROR("Invalid FW_CONFIG address\n");
197 plat_error_handler(err);
198 }
199
200 /* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
201 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
202 assert(desc != NULL);
203 desc->ep_info.args.arg0 = fw_config_info->config_addr;
Louis Mayencourt5a15b2d2019-10-17 14:46:51 +0100204
Manish V Badarkheeba13bd2022-01-08 23:08:02 +0000205#if CRYPTO_SUPPORT
John Tsichritzisc34341a2018-07-30 13:41:52 +0100206 /* Share the Mbed TLS heap info with other images */
207 arm_bl1_set_mbedtls_heap();
Manish V Badarkheeba13bd2022-01-08 23:08:02 +0000208#endif /* CRYPTO_SUPPORT */
Antonio Nino Diaz05f49572018-09-25 11:37:23 +0100209
Soby Mathewd969a7e2018-06-11 16:40:36 +0100210 /*
211 * Allow access to the System counter timer module and program
212 * counter frequency for non secure images during FWU
213 */
Usama Arife97998f2018-11-30 15:43:56 +0000214#ifdef ARM_SYS_TIMCTL_BASE
Soby Mathewd969a7e2018-06-11 16:40:36 +0100215 arm_configure_sys_timer();
Usama Arife97998f2018-11-30 15:43:56 +0000216#endif
Usama Arif078e66f2018-12-12 17:14:29 +0000217#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
Soby Mathewd969a7e2018-06-11 16:40:36 +0100218 write_cntfrq_el0(plat_get_syscnt_freq2());
Usama Arif078e66f2018-12-12 17:14:29 +0000219#endif
Dan Handley9df48042015-03-19 18:58:55 +0000220}
221
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000222void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
223{
Juan Castillob6132f12015-10-06 14:01:35 +0100224#if !ARM_DISABLE_TRUSTED_WDOG
225 /* Disable watchdog before leaving BL1 */
Aditya Angadi20b48412019-04-16 11:29:14 +0530226 plat_arm_secure_wdt_stop();
Juan Castillob6132f12015-10-06 14:01:35 +0100227#endif
228
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000229#ifdef EL3_PAYLOAD_BASE
230 /*
231 * Program the EL3 payload's entry point address into the CPUs mailbox
232 * in order to release secondary CPUs from their holding pen and make
233 * them jump there.
234 */
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100235 plat_arm_program_trusted_mailbox(ep_info->pc);
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000236 dsbsy();
237 sev();
238#endif
239}
Soby Mathew94273572018-03-07 11:32:04 +0000240
Sathees Balya22576072018-09-03 17:41:13 +0100241/*
242 * On Arm platforms, the FWU process is triggered when the FIP image has
243 * been tampered with.
244 */
Louis Mayencourt70d7c092020-01-29 11:42:31 +0000245bool plat_arm_bl1_fwu_needed(void)
Sathees Balya22576072018-09-03 17:41:13 +0100246{
Louis Mayencourt70d7c092020-01-29 11:42:31 +0000247 return !arm_io_is_toc_valid();
Sathees Balya22576072018-09-03 17:41:13 +0100248}
249
Soby Mathew94273572018-03-07 11:32:04 +0000250/*******************************************************************************
251 * The following function checks if Firmware update is needed,
252 * by checking if TOC in FIP image is valid or not.
253 ******************************************************************************/
254unsigned int bl1_plat_get_next_image_id(void)
255{
Manish V Badarkhebc4350b2020-07-14 11:28:36 +0100256 return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
Soby Mathew94273572018-03-07 11:32:04 +0000257}