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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7c6df5b2018-01-15 14:43:42 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
9#include <platform_def.h>
10
Dan Handley9df48042015-03-19 18:58:55 +000011#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <bl1/bl1.h>
13#include <common/bl_common.h>
14#include <drivers/arm/sp805.h>
15#include <lib/utils.h>
16#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000017#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018#include <plat/common/platform.h>
19
Dan Handley9df48042015-03-19 18:58:55 +000020/* Weak definitions may be overridden in specific ARM standard platform */
21#pragma weak bl1_early_platform_setup
22#pragma weak bl1_plat_arch_setup
23#pragma weak bl1_platform_setup
24#pragma weak bl1_plat_sec_mem_layout
Yatharth Kocharede39cb2016-11-14 12:01:04 +000025#pragma weak bl1_plat_prepare_exit
Sathees Balya22576072018-09-03 17:41:13 +010026#pragma weak bl1_plat_get_next_image_id
27#pragma weak plat_arm_bl1_fwu_needed
Dan Handley9df48042015-03-19 18:58:55 +000028
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010029#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
30 bl1_tzram_layout.total_base, \
31 bl1_tzram_layout.total_size, \
32 MT_MEMORY | MT_RW | MT_SECURE)
Daniel Boulby4e97abd2018-07-16 14:09:15 +010033/*
34 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
35 * otherwise one region is defined containing both
36 */
37#if SEPARATE_CODE_AND_RODATA
38#define MAP_BL1_RO MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010039 BL_CODE_BASE, \
40 BL1_CODE_END - BL_CODE_BASE, \
Daniel Boulby4e97abd2018-07-16 14:09:15 +010041 MT_CODE | MT_SECURE), \
42 MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010043 BL1_RO_DATA_BASE, \
44 BL1_RO_DATA_END \
45 - BL_RO_DATA_BASE, \
46 MT_RO_DATA | MT_SECURE)
Daniel Boulby4e97abd2018-07-16 14:09:15 +010047#else
48#define MAP_BL1_RO MAP_REGION_FLAT( \
49 BL_CODE_BASE, \
50 BL1_CODE_END - BL_CODE_BASE, \
51 MT_CODE | MT_SECURE)
52#endif
Dan Handley9df48042015-03-19 18:58:55 +000053
54/* Data structure which holds the extents of the trusted SRAM for BL1*/
55static meminfo_t bl1_tzram_layout;
56
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020057struct meminfo *bl1_plat_sec_mem_layout(void)
Dan Handley9df48042015-03-19 18:58:55 +000058{
59 return &bl1_tzram_layout;
60}
61
62/*******************************************************************************
63 * BL1 specific platform actions shared between ARM standard platforms.
64 ******************************************************************************/
65void arm_bl1_early_platform_setup(void)
66{
Dan Handley9df48042015-03-19 18:58:55 +000067
Juan Castillob6132f12015-10-06 14:01:35 +010068#if !ARM_DISABLE_TRUSTED_WDOG
69 /* Enable watchdog */
70 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
71#endif
72
Dan Handley9df48042015-03-19 18:58:55 +000073 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010074 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000075
76 /* Allow BL1 to see the whole Trusted RAM */
77 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
78 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
Dan Handley9df48042015-03-19 18:58:55 +000079}
80
81void bl1_early_platform_setup(void)
82{
83 arm_bl1_early_platform_setup();
84
85 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000086 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +000087 * No need for locks as no other CPU is active.
88 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000089 plat_arm_interconnect_init();
Dan Handley9df48042015-03-19 18:58:55 +000090 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000091 * Enable Interconnect coherency for the primary CPU's cluster.
Dan Handley9df48042015-03-19 18:58:55 +000092 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000093 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +000094}
95
96/******************************************************************************
97 * Perform the very early platform specific architecture setup shared between
98 * ARM standard platforms. This only does basic initialization. Later
99 * architectural setup (bl1_arch_setup()) does not do anything platform
100 * specific.
101 *****************************************************************************/
102void arm_bl1_plat_arch_setup(void)
103{
Soby Mathewb9856482018-09-18 11:42:42 +0100104#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
105 /*
106 * Ensure ARM platforms don't use coherent memory in BL1 unless
107 * cryptocell integration is enabled.
108 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100109 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000110#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100111
112 const mmap_region_t bl_regions[] = {
113 MAP_BL1_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100114 MAP_BL1_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100115#if USE_ROMLIB
116 ARM_MAP_ROMLIB_CODE,
117 ARM_MAP_ROMLIB_DATA,
Soby Mathewb9856482018-09-18 11:42:42 +0100118#endif
119#if ARM_CRYPTOCELL_INTEG
120 ARM_MAP_BL_COHERENT_RAM,
121#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100122 {0}
123 };
124
Roberto Vargas344ff022018-10-19 16:44:18 +0100125 setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100126#ifdef AARCH32
Antonio Nino Diaz533d3a82018-08-07 16:35:19 +0100127 enable_mmu_svc_mon(0);
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100128#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100129 enable_mmu_el3(0);
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100130#endif /* AARCH32 */
Roberto Vargase3adc372018-05-23 09:27:06 +0100131
132 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000133}
134
135void bl1_plat_arch_setup(void)
136{
137 arm_bl1_plat_arch_setup();
138}
139
140/*
141 * Perform the platform specific architecture setup shared between
142 * ARM standard platforms.
143 */
144void arm_bl1_platform_setup(void)
145{
146 /* Initialise the IO layer and register platform IO devices */
147 plat_arm_io_setup();
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000148 arm_load_tb_fw_config();
John Tsichritzisc34341a2018-07-30 13:41:52 +0100149#if TRUSTED_BOARD_BOOT
150 /* Share the Mbed TLS heap info with other images */
151 arm_bl1_set_mbedtls_heap();
152#endif /* TRUSTED_BOARD_BOOT */
Antonio Nino Diaz05f49572018-09-25 11:37:23 +0100153
Soby Mathewd969a7e2018-06-11 16:40:36 +0100154 /*
155 * Allow access to the System counter timer module and program
156 * counter frequency for non secure images during FWU
157 */
Usama Arife97998f2018-11-30 15:43:56 +0000158#ifdef ARM_SYS_TIMCTL_BASE
Soby Mathewd969a7e2018-06-11 16:40:36 +0100159 arm_configure_sys_timer();
Usama Arife97998f2018-11-30 15:43:56 +0000160#endif
Usama Arif078e66f2018-12-12 17:14:29 +0000161#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
Soby Mathewd969a7e2018-06-11 16:40:36 +0100162 write_cntfrq_el0(plat_get_syscnt_freq2());
Usama Arif078e66f2018-12-12 17:14:29 +0000163#endif
Dan Handley9df48042015-03-19 18:58:55 +0000164}
165
166void bl1_platform_setup(void)
167{
168 arm_bl1_platform_setup();
169}
170
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000171void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
172{
Juan Castillob6132f12015-10-06 14:01:35 +0100173#if !ARM_DISABLE_TRUSTED_WDOG
174 /* Disable watchdog before leaving BL1 */
175 sp805_stop(ARM_SP805_TWDG_BASE);
176#endif
177
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000178#ifdef EL3_PAYLOAD_BASE
179 /*
180 * Program the EL3 payload's entry point address into the CPUs mailbox
181 * in order to release secondary CPUs from their holding pen and make
182 * them jump there.
183 */
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100184 plat_arm_program_trusted_mailbox(ep_info->pc);
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000185 dsbsy();
186 sev();
187#endif
188}
Soby Mathew94273572018-03-07 11:32:04 +0000189
Sathees Balya22576072018-09-03 17:41:13 +0100190/*
191 * On Arm platforms, the FWU process is triggered when the FIP image has
192 * been tampered with.
193 */
194int plat_arm_bl1_fwu_needed(void)
195{
196 return (arm_io_is_toc_valid() != 1);
197}
198
Soby Mathew94273572018-03-07 11:32:04 +0000199/*******************************************************************************
200 * The following function checks if Firmware update is needed,
201 * by checking if TOC in FIP image is valid or not.
202 ******************************************************************************/
203unsigned int bl1_plat_get_next_image_id(void)
204{
Sathees Balya22576072018-09-03 17:41:13 +0100205 if (plat_arm_bl1_fwu_needed() != 0)
Soby Mathew94273572018-03-07 11:32:04 +0000206 return NS_BL1U_IMAGE_ID;
207
208 return BL2_IMAGE_ID;
209}