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Varun Wadekarecd6a5a2018-04-09 17:48:58 -07001/*
2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __TEGRA_DEF_H__
8#define __TEGRA_DEF_H__
9
10#include <lib/utils_def.h>
11
12/*******************************************************************************
13 * These values are used by the PSCI implementation during the `CPU_SUSPEND`
14 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
15 * parameter.
16 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080017#define PSTATE_ID_CORE_IDLE U(6)
18#define PSTATE_ID_CORE_POWERDN U(7)
19#define PSTATE_ID_SOC_POWERDN U(2)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070020
21/*******************************************************************************
22 * Platform power states (used by PSCI framework)
23 *
24 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
25 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
26 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080027#define PLAT_MAX_RET_STATE U(1)
28#define PLAT_MAX_OFF_STATE U(8)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070029
30/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070031 * Secure IRQ definitions
32 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -080033#define TEGRA194_MAX_SEC_IRQS U(2)
34#define TEGRA194_TOP_WDT_IRQ U(49)
35#define TEGRA194_AON_WDT_IRQ U(50)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070036
Varun Wadekar362a6b22017-11-10 11:04:42 -080037#define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070038
39/*******************************************************************************
40 * Tegra Miscellanous register constants
41 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080042#define TEGRA_MISC_BASE U(0x00100000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070043
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080044#define HARDWARE_REVISION_OFFSET U(0x4)
45#define MISCREG_EMU_REVID U(0x3160)
46#define BOARD_MASK_BITS U(0xFF)
47#define BOARD_SHIFT_BITS U(24)
48#define MISCREG_PFCFG U(0x200C)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070049
50/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070051 * Tegra Memory Controller constants
52 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080053#define TEGRA_MC_STREAMID_BASE U(0x02C00000)
54#define TEGRA_MC_BASE U(0x02C10000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070055
Varun Wadekar07897a92017-02-13 09:00:04 -080056/* General Security Carveout register macros */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080057#define MC_GSC_CONFIG_REGS_SIZE U(0x40)
58#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
59#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0)
60#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
61#define MC_GSC_BASE_LO_SHIFT U(12)
62#define MC_GSC_BASE_LO_MASK U(0xFFFFF)
63#define MC_GSC_BASE_HI_SHIFT U(0)
64#define MC_GSC_BASE_HI_MASK U(3)
Varun Wadekar4309d7b2017-10-03 15:25:44 -070065#define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31)
Varun Wadekar07897a92017-02-13 09:00:04 -080066
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070067/* TZDRAM carveout configuration registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080068#define MC_SECURITY_CFG0_0 U(0x70)
69#define MC_SECURITY_CFG1_0 U(0x74)
70#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070071
Harvey Hsieh53fc0322017-08-09 16:26:33 +080072#define MC_SECURITY_BOM_MASK (U(0xFFF) << 20)
73#define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0)
74#define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0)
75
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070076/* Video Memory carveout configuration registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080077#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
78#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
79#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070080
Varun Wadekar07897a92017-02-13 09:00:04 -080081/*
82 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
83 * non-overlapping Video memory region
84 */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080085#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
86#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
87#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
88#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
89#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
Varun Wadekar07897a92017-02-13 09:00:04 -080090
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070091/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080092#define MC_TZRAM_CARVEOUT_CFG U(0x2190)
93#define MC_TZRAM_BASE_LO U(0x2194)
94#define MC_TZRAM_BASE_HI U(0x2198)
95#define MC_TZRAM_SIZE U(0x219C)
Varun Wadekar4309d7b2017-10-03 15:25:44 -070096#define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0)
97#define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4)
98#define TZRAM_ALLOW_MPCORER (U(1) << 7)
99#define TZRAM_ALLOW_MPCOREW (U(1) << 25)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700100
101/* Memory Controller Reset Control registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800102#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28)
103#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29)
104#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30)
105#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700106
107/*******************************************************************************
108 * Tegra UART Controller constants
109 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800110#define TEGRA_UARTA_BASE U(0x03100000)
111#define TEGRA_UARTB_BASE U(0x03110000)
112#define TEGRA_UARTC_BASE U(0x0C280000)
113#define TEGRA_UARTD_BASE U(0x03130000)
114#define TEGRA_UARTE_BASE U(0x03140000)
115#define TEGRA_UARTF_BASE U(0x03150000)
116#define TEGRA_UARTG_BASE U(0x0C290000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700117
118/*******************************************************************************
119 * Tegra Fuse Controller related constants
120 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800121#define TEGRA_FUSE_BASE U(0x03820000)
122#define OPT_SUBREVISION U(0x248)
123#define SUBREVISION_MASK U(0xF)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700124
125/*******************************************************************************
126 * GICv2 & interrupt handling related constants
127 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800128#define TEGRA_GICD_BASE U(0x03881000)
129#define TEGRA_GICC_BASE U(0x03882000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700130
131/*******************************************************************************
132 * Security Engine related constants
133 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800134#define TEGRA_SE0_BASE U(0x03AC0000)
Steven Kao530b2172017-06-23 16:18:58 +0800135#define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
136#define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC)
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800137#define TEGRA_PKA1_BASE U(0x03AD0000)
Steven Kao530b2172017-06-23 16:18:58 +0800138#define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144)
139#define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800140#define TEGRA_RNG1_BASE U(0x03AE0000)
Steven Kao530b2172017-06-23 16:18:58 +0800141#define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700142
143/*******************************************************************************
144 * Tegra micro-seconds timer constants
145 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800146#define TEGRA_TMRUS_BASE U(0x0C2E0000)
147#define TEGRA_TMRUS_SIZE U(0x10000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700148
149/*******************************************************************************
150 * Tegra Power Mgmt Controller constants
151 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800152#define TEGRA_PMC_BASE U(0x0C360000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700153
154/*******************************************************************************
155 * Tegra scratch registers constants
156 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800157#define TEGRA_SCRATCH_BASE U(0x0C390000)
Steven Kao4607f172017-10-23 18:35:14 +0800158#define SECURE_SCRATCH_RSV44_LO U(0x1C4)
159#define SECURE_SCRATCH_RSV44_HI U(0x1C8)
160#define SECURE_SCRATCH_RSV97 U(0x36C)
161#define SECURE_SCRATCH_RSV99_LO U(0x37C)
162#define SECURE_SCRATCH_RSV99_HI U(0x380)
163#define SECURE_SCRATCH_RSV109_LO U(0x3CC)
164#define SECURE_SCRATCH_RSV109_HI U(0x3D0)
165
166#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV44_LO
167#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV44_HI
168#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97
169#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO
170#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI
171#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO
172#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700173
174/*******************************************************************************
175 * Tegra Memory Mapped Control Register Access Bus constants
176 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800177#define TEGRA_MMCRAB_BASE U(0x0E000000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700178
179/*******************************************************************************
180 * Tegra SMMU Controller constants
181 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800182#define TEGRA_SMMU0_BASE U(0x12000000)
183#define TEGRA_SMMU1_BASE U(0x11000000)
184#define TEGRA_SMMU2_BASE U(0x10000000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700185
186/*******************************************************************************
187 * Tegra TZRAM constants
188 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800189#define TEGRA_TZRAM_BASE U(0x40000000)
190#define TEGRA_TZRAM_SIZE U(0x40000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700191
192/*******************************************************************************
193 * Tegra Clock and Reset Controller constants
194 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800195#define TEGRA_CAR_RESET_BASE U(0x20000000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700196
Varun Wadekar00759902017-05-31 11:41:00 -0700197/*******************************************************************************
Ajay Gupta81621092017-08-01 15:53:04 -0700198 * XUSB PADCTL
199 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800200#define TEGRA_XUSB_PADCTL_BASE U(0x3520000)
201#define TEGRA_XUSB_PADCTL_SIZE U(0x10000)
202#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c)
203#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370)
204#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374)
205#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378)
206#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c)
207#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c)
Ajay Gupta81621092017-08-01 15:53:04 -0700208
209/*******************************************************************************
210 * XUSB STREAMIDs
211 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800212#define TEGRA_SID_XUSB_HOST U(0x1b)
213#define TEGRA_SID_XUSB_DEV U(0x1c)
214#define TEGRA_SID_XUSB_VF0 U(0x5d)
215#define TEGRA_SID_XUSB_VF1 U(0x5e)
216#define TEGRA_SID_XUSB_VF2 U(0x5f)
217#define TEGRA_SID_XUSB_VF3 U(0x60)
Ajay Gupta81621092017-08-01 15:53:04 -0700218
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700219#endif /* __TEGRA_DEF_H__ */