Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 2 | * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 5ee3abc | 2018-06-12 16:49:12 -0700 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 6 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 7 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 8 | #include <asm_macros.S> |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 9 | #include <assert_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <common/bl_common.h> |
| 11 | #include <common/debug.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 12 | #include <cortex_a57.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 13 | #include <cpu_macros.S> |
| 14 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 15 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 16 | /* --------------------------------------------- |
| 17 | * Disable L1 data cache and unified L2 cache |
| 18 | * --------------------------------------------- |
| 19 | */ |
| 20 | func cortex_a57_disable_dcache |
| 21 | mrs x1, sctlr_el3 |
| 22 | bic x1, x1, #SCTLR_C_BIT |
| 23 | msr sctlr_el3, x1 |
| 24 | isb |
| 25 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 26 | endfunc cortex_a57_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 27 | |
| 28 | /* --------------------------------------------- |
| 29 | * Disable all types of L2 prefetches. |
| 30 | * --------------------------------------------- |
| 31 | */ |
| 32 | func cortex_a57_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 33 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 34 | orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 35 | mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK |
| 36 | orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 37 | bic x0, x0, x1 |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 38 | msr CORTEX_A57_ECTLR_EL1, x0 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 39 | isb |
Soby Mathew | 1604fa0 | 2014-09-22 12:15:26 +0100 | [diff] [blame] | 40 | dsb ish |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 41 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 42 | endfunc cortex_a57_disable_l2_prefetch |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 43 | |
| 44 | /* --------------------------------------------- |
| 45 | * Disable intra-cluster coherency |
| 46 | * --------------------------------------------- |
| 47 | */ |
| 48 | func cortex_a57_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 49 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 50 | bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT |
| 51 | msr CORTEX_A57_ECTLR_EL1, x0 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 52 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 53 | endfunc cortex_a57_disable_smp |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 54 | |
| 55 | /* --------------------------------------------- |
| 56 | * Disable debug interfaces |
| 57 | * --------------------------------------------- |
| 58 | */ |
| 59 | func cortex_a57_disable_ext_debug |
| 60 | mov x0, #1 |
| 61 | msr osdlr_el1, x0 |
| 62 | isb |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 63 | #if ERRATA_A57_817169 |
| 64 | /* |
| 65 | * Invalidate any TLB address |
| 66 | */ |
| 67 | mov x0, #0 |
| 68 | tlbi vae3, x0 |
| 69 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 70 | dsb sy |
| 71 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 72 | endfunc cortex_a57_disable_ext_debug |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 73 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 74 | /* -------------------------------------------------- |
| 75 | * Errata Workaround for Cortex A57 Errata #806969. |
| 76 | * This applies only to revision r0p0 of Cortex A57. |
| 77 | * Inputs: |
| 78 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 79 | * Shall clobber: x0-x17 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 80 | * -------------------------------------------------- |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 81 | */ |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 82 | func errata_a57_806969_wa |
| 83 | /* |
| 84 | * Compare x0 against revision r0p0 |
| 85 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 86 | mov x17, x30 |
| 87 | bl check_errata_806969 |
| 88 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 89 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 90 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA |
| 91 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 92 | 1: |
| 93 | ret x17 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 94 | endfunc errata_a57_806969_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 95 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 96 | func check_errata_806969 |
| 97 | mov x1, #0x00 |
| 98 | b cpu_rev_var_ls |
| 99 | endfunc check_errata_806969 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 100 | |
| 101 | /* --------------------------------------------------- |
Antonio Nino Diaz | 3f13c35 | 2017-02-24 11:39:22 +0000 | [diff] [blame] | 102 | * Errata Workaround for Cortex A57 Errata #813419. |
| 103 | * This applies only to revision r0p0 of Cortex A57. |
| 104 | * --------------------------------------------------- |
| 105 | */ |
| 106 | func check_errata_813419 |
| 107 | /* |
| 108 | * Even though this is only needed for revision r0p0, it |
| 109 | * is always applied due to limitations of the current |
| 110 | * errata framework. |
| 111 | */ |
| 112 | mov x0, #ERRATA_APPLIES |
| 113 | ret |
| 114 | endfunc check_errata_813419 |
| 115 | |
| 116 | /* --------------------------------------------------- |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 117 | * Errata Workaround for Cortex A57 Errata #813420. |
| 118 | * This applies only to revision r0p0 of Cortex A57. |
| 119 | * Inputs: |
| 120 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 121 | * Shall clobber: x0-x17 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 122 | * --------------------------------------------------- |
| 123 | */ |
| 124 | func errata_a57_813420_wa |
| 125 | /* |
| 126 | * Compare x0 against revision r0p0 |
| 127 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 128 | mov x17, x30 |
| 129 | bl check_errata_813420 |
| 130 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 131 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 132 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI |
| 133 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 134 | 1: |
| 135 | ret x17 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 136 | endfunc errata_a57_813420_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 137 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 138 | func check_errata_813420 |
| 139 | mov x1, #0x00 |
| 140 | b cpu_rev_var_ls |
| 141 | endfunc check_errata_813420 |
| 142 | |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 143 | /* --------------------------------------------------- |
| 144 | * Errata Workaround for Cortex A57 Errata #814670. |
| 145 | * This applies only to revision r0p0 of Cortex A57. |
| 146 | * Inputs: |
| 147 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 148 | * Shall clobber: x0-x17 |
| 149 | * --------------------------------------------------- |
| 150 | */ |
| 151 | func errata_a57_814670_wa |
| 152 | /* |
| 153 | * Compare x0 against revision r0p0 |
| 154 | */ |
| 155 | mov x17, x30 |
| 156 | bl check_errata_814670 |
| 157 | cbz x0, 1f |
| 158 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 159 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION |
| 160 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
| 161 | isb |
| 162 | 1: |
| 163 | ret x17 |
| 164 | endfunc errata_a57_814670_wa |
| 165 | |
| 166 | func check_errata_814670 |
| 167 | mov x1, #0x00 |
| 168 | b cpu_rev_var_ls |
| 169 | endfunc check_errata_814670 |
| 170 | |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 171 | /* ---------------------------------------------------- |
| 172 | * Errata Workaround for Cortex A57 Errata #817169. |
| 173 | * This applies only to revision <= r0p1 of Cortex A57. |
| 174 | * ---------------------------------------------------- |
| 175 | */ |
| 176 | func check_errata_817169 |
| 177 | /* |
| 178 | * Even though this is only needed for revision <= r0p1, it |
| 179 | * is always applied because of the low cost of the workaround. |
| 180 | */ |
| 181 | mov x0, #ERRATA_APPLIES |
| 182 | ret |
| 183 | endfunc check_errata_817169 |
| 184 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 185 | /* -------------------------------------------------------------------- |
| 186 | * Disable the over-read from the LDNP instruction. |
| 187 | * |
| 188 | * This applies to all revisions <= r1p2. The performance degradation |
| 189 | * observed with LDNP/STNP has been fixed on r1p3 and onwards. |
| 190 | * |
| 191 | * Inputs: |
| 192 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 193 | * Shall clobber: x0-x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 194 | * --------------------------------------------------------------------- |
| 195 | */ |
| 196 | func a57_disable_ldnp_overread |
| 197 | /* |
| 198 | * Compare x0 against revision r1p2 |
| 199 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 200 | mov x17, x30 |
| 201 | bl check_errata_disable_ldnp_overread |
| 202 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 203 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 204 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD |
| 205 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 206 | 1: |
| 207 | ret x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 208 | endfunc a57_disable_ldnp_overread |
| 209 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 210 | func check_errata_disable_ldnp_overread |
| 211 | mov x1, #0x12 |
| 212 | b cpu_rev_var_ls |
| 213 | endfunc check_errata_disable_ldnp_overread |
| 214 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 215 | /* --------------------------------------------------- |
| 216 | * Errata Workaround for Cortex A57 Errata #826974. |
| 217 | * This applies only to revision <= r1p1 of Cortex A57. |
| 218 | * Inputs: |
| 219 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 220 | * Shall clobber: x0-x17 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 221 | * --------------------------------------------------- |
| 222 | */ |
| 223 | func errata_a57_826974_wa |
| 224 | /* |
| 225 | * Compare x0 against revision r1p1 |
| 226 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 227 | mov x17, x30 |
| 228 | bl check_errata_826974 |
| 229 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 230 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 231 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB |
| 232 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 233 | 1: |
| 234 | ret x17 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 235 | endfunc errata_a57_826974_wa |
| 236 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 237 | func check_errata_826974 |
| 238 | mov x1, #0x11 |
| 239 | b cpu_rev_var_ls |
| 240 | endfunc check_errata_826974 |
| 241 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 242 | /* --------------------------------------------------- |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 243 | * Errata Workaround for Cortex A57 Errata #826977. |
| 244 | * This applies only to revision <= r1p1 of Cortex A57. |
| 245 | * Inputs: |
| 246 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 247 | * Shall clobber: x0-x17 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 248 | * --------------------------------------------------- |
| 249 | */ |
| 250 | func errata_a57_826977_wa |
| 251 | /* |
| 252 | * Compare x0 against revision r1p1 |
| 253 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 254 | mov x17, x30 |
| 255 | bl check_errata_826977 |
| 256 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 257 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 258 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE |
| 259 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 260 | 1: |
| 261 | ret x17 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 262 | endfunc errata_a57_826977_wa |
| 263 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 264 | func check_errata_826977 |
| 265 | mov x1, #0x11 |
| 266 | b cpu_rev_var_ls |
| 267 | endfunc check_errata_826977 |
| 268 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 269 | /* --------------------------------------------------- |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 270 | * Errata Workaround for Cortex A57 Errata #828024. |
| 271 | * This applies only to revision <= r1p1 of Cortex A57. |
| 272 | * Inputs: |
| 273 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 274 | * Shall clobber: x0-x17 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 275 | * --------------------------------------------------- |
| 276 | */ |
| 277 | func errata_a57_828024_wa |
| 278 | /* |
| 279 | * Compare x0 against revision r1p1 |
| 280 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 281 | mov x17, x30 |
| 282 | bl check_errata_828024 |
| 283 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 284 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 285 | /* |
| 286 | * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 |
| 287 | * instructions here because the resulting bitmask doesn't fit in a |
| 288 | * 16-bit value so it cannot be encoded in a single instruction. |
| 289 | */ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 290 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA |
| 291 | orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \ |
| 292 | CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING) |
| 293 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 294 | 1: |
| 295 | ret x17 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 296 | endfunc errata_a57_828024_wa |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 297 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 298 | func check_errata_828024 |
| 299 | mov x1, #0x11 |
| 300 | b cpu_rev_var_ls |
| 301 | endfunc check_errata_828024 |
| 302 | |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 303 | /* --------------------------------------------------- |
| 304 | * Errata Workaround for Cortex A57 Errata #829520. |
| 305 | * This applies only to revision <= r1p2 of Cortex A57. |
| 306 | * Inputs: |
| 307 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 308 | * Shall clobber: x0-x17 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 309 | * --------------------------------------------------- |
| 310 | */ |
| 311 | func errata_a57_829520_wa |
| 312 | /* |
| 313 | * Compare x0 against revision r1p2 |
| 314 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 315 | mov x17, x30 |
| 316 | bl check_errata_829520 |
| 317 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 318 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 319 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR |
| 320 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 321 | 1: |
| 322 | ret x17 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 323 | endfunc errata_a57_829520_wa |
| 324 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 325 | func check_errata_829520 |
| 326 | mov x1, #0x12 |
| 327 | b cpu_rev_var_ls |
| 328 | endfunc check_errata_829520 |
| 329 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 330 | /* --------------------------------------------------- |
| 331 | * Errata Workaround for Cortex A57 Errata #833471. |
| 332 | * This applies only to revision <= r1p2 of Cortex A57. |
| 333 | * Inputs: |
| 334 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 335 | * Shall clobber: x0-x17 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 336 | * --------------------------------------------------- |
| 337 | */ |
| 338 | func errata_a57_833471_wa |
| 339 | /* |
| 340 | * Compare x0 against revision r1p2 |
| 341 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 342 | mov x17, x30 |
| 343 | bl check_errata_833471 |
| 344 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 345 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 346 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH |
| 347 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 348 | 1: |
| 349 | ret x17 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 350 | endfunc errata_a57_833471_wa |
| 351 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 352 | func check_errata_833471 |
| 353 | mov x1, #0x12 |
| 354 | b cpu_rev_var_ls |
| 355 | endfunc check_errata_833471 |
| 356 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 357 | /* -------------------------------------------------- |
| 358 | * Errata Workaround for Cortex A57 Errata #859972. |
| 359 | * This applies only to revision <= r1p3 of Cortex A57. |
| 360 | * Inputs: |
| 361 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 362 | * Shall clobber: |
| 363 | * -------------------------------------------------- |
| 364 | */ |
| 365 | func errata_a57_859972_wa |
| 366 | mov x17, x30 |
| 367 | bl check_errata_859972 |
| 368 | cbz x0, 1f |
| 369 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 370 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH |
| 371 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
| 372 | 1: |
| 373 | ret x17 |
| 374 | endfunc errata_a57_859972_wa |
| 375 | |
| 376 | func check_errata_859972 |
| 377 | mov x1, #0x13 |
| 378 | b cpu_rev_var_ls |
| 379 | endfunc check_errata_859972 |
| 380 | |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 381 | func check_errata_cve_2017_5715 |
| 382 | #if WORKAROUND_CVE_2017_5715 |
| 383 | mov x0, #ERRATA_APPLIES |
| 384 | #else |
| 385 | mov x0, #ERRATA_MISSING |
| 386 | #endif |
| 387 | ret |
| 388 | endfunc check_errata_cve_2017_5715 |
| 389 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 390 | func check_errata_cve_2018_3639 |
| 391 | #if WORKAROUND_CVE_2018_3639 |
| 392 | mov x0, #ERRATA_APPLIES |
| 393 | #else |
| 394 | mov x0, #ERRATA_MISSING |
| 395 | #endif |
| 396 | ret |
| 397 | endfunc check_errata_cve_2018_3639 |
| 398 | |
Manish V Badarkhe | 7672edf | 2020-08-03 18:43:14 +0100 | [diff] [blame] | 399 | /* -------------------------------------------------- |
| 400 | * Errata workaround for Cortex A57 Errata #1319537. |
| 401 | * This applies to all revisions of Cortex A57. |
| 402 | * -------------------------------------------------- |
| 403 | */ |
| 404 | func check_errata_1319537 |
| 405 | #if ERRATA_A57_1319537 |
| 406 | mov x0, #ERRATA_APPLIES |
| 407 | #else |
| 408 | mov x0, #ERRATA_MISSING |
| 409 | #endif |
| 410 | ret |
| 411 | endfunc check_errata_1319537 |
| 412 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 413 | /* ------------------------------------------------- |
| 414 | * The CPU Ops reset function for Cortex-A57. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 415 | * Shall clobber: x0-x19 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 416 | * ------------------------------------------------- |
| 417 | */ |
| 418 | func cortex_a57_reset_func |
| 419 | mov x19, x30 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 420 | bl cpu_get_rev_var |
| 421 | mov x18, x0 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 422 | |
| 423 | #if ERRATA_A57_806969 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 424 | mov x0, x18 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 425 | bl errata_a57_806969_wa |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 426 | #endif |
| 427 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 428 | #if ERRATA_A57_813420 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 429 | mov x0, x18 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 430 | bl errata_a57_813420_wa |
| 431 | #endif |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 432 | |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 433 | #if ERRATA_A57_814670 |
| 434 | mov x0, x18 |
| 435 | bl errata_a57_814670_wa |
| 436 | #endif |
| 437 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 438 | #if A57_DISABLE_NON_TEMPORAL_HINT |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 439 | mov x0, x18 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 440 | bl a57_disable_ldnp_overread |
| 441 | #endif |
| 442 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 443 | #if ERRATA_A57_826974 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 444 | mov x0, x18 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 445 | bl errata_a57_826974_wa |
| 446 | #endif |
| 447 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 448 | #if ERRATA_A57_826977 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 449 | mov x0, x18 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 450 | bl errata_a57_826977_wa |
| 451 | #endif |
| 452 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 453 | #if ERRATA_A57_828024 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 454 | mov x0, x18 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 455 | bl errata_a57_828024_wa |
| 456 | #endif |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 457 | |
| 458 | #if ERRATA_A57_829520 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 459 | mov x0, x18 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 460 | bl errata_a57_829520_wa |
| 461 | #endif |
| 462 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 463 | #if ERRATA_A57_833471 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 464 | mov x0, x18 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 465 | bl errata_a57_833471_wa |
| 466 | #endif |
| 467 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 468 | #if ERRATA_A57_859972 |
| 469 | mov x0, x18 |
| 470 | bl errata_a57_859972_wa |
| 471 | #endif |
| 472 | |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame] | 473 | #if IMAGE_BL31 && ( WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 ) |
| 474 | /* --------------------------------------------------------------- |
| 475 | * Override vector table & enable existing workaround if either of |
| 476 | * the build flags are enabled |
| 477 | * --------------------------------------------------------------- |
| 478 | */ |
Dimitris Papastamos | 570c06a | 2018-04-06 15:29:34 +0100 | [diff] [blame] | 479 | adr x0, wa_cve_2017_5715_mmu_vbar |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 480 | msr vbar_el3, x0 |
Dimitris Papastamos | bb0aa39 | 2018-06-07 13:20:19 +0100 | [diff] [blame] | 481 | /* isb will be performed before returning from this function */ |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 482 | #endif |
| 483 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 484 | #if WORKAROUND_CVE_2018_3639 |
| 485 | mrs x0, CORTEX_A57_CPUACTLR_EL1 |
| 486 | orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE |
| 487 | msr CORTEX_A57_CPUACTLR_EL1, x0 |
| 488 | isb |
| 489 | dsb sy |
| 490 | #endif |
| 491 | |
Varun Wadekar | 5ee3abc | 2018-06-12 16:49:12 -0700 | [diff] [blame] | 492 | #if A57_ENABLE_NONCACHEABLE_LOAD_FWD |
| 493 | /* --------------------------------------------- |
| 494 | * Enable higher performance non-cacheable load |
| 495 | * forwarding |
| 496 | * --------------------------------------------- |
| 497 | */ |
| 498 | mrs x0, CORTEX_A57_CPUACTLR_EL1 |
| 499 | orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD |
| 500 | msr CORTEX_A57_CPUACTLR_EL1, x0 |
| 501 | #endif |
| 502 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 503 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 504 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 505 | * --------------------------------------------- |
| 506 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 507 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 508 | orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT |
| 509 | msr CORTEX_A57_ECTLR_EL1, x0 |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 510 | isb |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 511 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 512 | endfunc cortex_a57_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 513 | |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame] | 514 | func check_errata_cve_2022_23960 |
| 515 | #if WORKAROUND_CVE_2022_23960 |
| 516 | mov x0, #ERRATA_APPLIES |
| 517 | #else |
| 518 | mov x0, #ERRATA_MISSING |
| 519 | #endif |
| 520 | ret |
| 521 | endfunc check_errata_cve_2022_23960 |
| 522 | |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 523 | func check_smccc_arch_workaround_3 |
| 524 | mov x0, #ERRATA_APPLIES |
| 525 | ret |
| 526 | endfunc check_smccc_arch_workaround_3 |
| 527 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 528 | /* ---------------------------------------------------- |
| 529 | * The CPU Ops core power down function for Cortex-A57. |
| 530 | * ---------------------------------------------------- |
| 531 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 532 | func cortex_a57_core_pwr_dwn |
| 533 | mov x18, x30 |
| 534 | |
| 535 | /* --------------------------------------------- |
| 536 | * Turn off caches. |
| 537 | * --------------------------------------------- |
| 538 | */ |
| 539 | bl cortex_a57_disable_dcache |
| 540 | |
| 541 | /* --------------------------------------------- |
| 542 | * Disable the L2 prefetches. |
| 543 | * --------------------------------------------- |
| 544 | */ |
| 545 | bl cortex_a57_disable_l2_prefetch |
| 546 | |
| 547 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 548 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 549 | * --------------------------------------------- |
| 550 | */ |
| 551 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 552 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 553 | |
| 554 | /* --------------------------------------------- |
| 555 | * Come out of intra cluster coherency |
| 556 | * --------------------------------------------- |
| 557 | */ |
| 558 | bl cortex_a57_disable_smp |
| 559 | |
| 560 | /* --------------------------------------------- |
| 561 | * Force the debug interfaces to be quiescent |
| 562 | * --------------------------------------------- |
| 563 | */ |
| 564 | mov x30, x18 |
| 565 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 566 | endfunc cortex_a57_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 567 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 568 | /* ------------------------------------------------------- |
| 569 | * The CPU Ops cluster power down function for Cortex-A57. |
| 570 | * ------------------------------------------------------- |
| 571 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 572 | func cortex_a57_cluster_pwr_dwn |
| 573 | mov x18, x30 |
| 574 | |
| 575 | /* --------------------------------------------- |
| 576 | * Turn off caches. |
| 577 | * --------------------------------------------- |
| 578 | */ |
| 579 | bl cortex_a57_disable_dcache |
| 580 | |
| 581 | /* --------------------------------------------- |
| 582 | * Disable the L2 prefetches. |
| 583 | * --------------------------------------------- |
| 584 | */ |
| 585 | bl cortex_a57_disable_l2_prefetch |
| 586 | |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 587 | #if !SKIP_A57_L1_FLUSH_PWR_DWN |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 588 | /* ------------------------------------------------- |
| 589 | * Flush the L1 caches. |
| 590 | * ------------------------------------------------- |
| 591 | */ |
| 592 | mov x0, #DCCISW |
| 593 | bl dcsw_op_level1 |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 594 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 595 | /* --------------------------------------------- |
| 596 | * Disable the optional ACP. |
| 597 | * --------------------------------------------- |
| 598 | */ |
| 599 | bl plat_disable_acp |
| 600 | |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 601 | /* ------------------------------------------------- |
| 602 | * Flush the L2 caches. |
| 603 | * ------------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 604 | */ |
| 605 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 606 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 607 | |
| 608 | /* --------------------------------------------- |
| 609 | * Come out of intra cluster coherency |
| 610 | * --------------------------------------------- |
| 611 | */ |
| 612 | bl cortex_a57_disable_smp |
| 613 | |
| 614 | /* --------------------------------------------- |
| 615 | * Force the debug interfaces to be quiescent |
| 616 | * --------------------------------------------- |
| 617 | */ |
| 618 | mov x30, x18 |
| 619 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 620 | endfunc cortex_a57_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 621 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 622 | #if REPORT_ERRATA |
| 623 | /* |
| 624 | * Errata printing function for Cortex A57. Must follow AAPCS. |
| 625 | */ |
| 626 | func cortex_a57_errata_report |
| 627 | stp x8, x30, [sp, #-16]! |
| 628 | |
| 629 | bl cpu_get_rev_var |
| 630 | mov x8, x0 |
| 631 | |
| 632 | /* |
| 633 | * Report all errata. The revision-variant information is passed to |
| 634 | * checking functions of each errata. |
| 635 | */ |
| 636 | report_errata ERRATA_A57_806969, cortex_a57, 806969 |
Antonio Nino Diaz | 3f13c35 | 2017-02-24 11:39:22 +0000 | [diff] [blame] | 637 | report_errata ERRATA_A57_813419, cortex_a57, 813419 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 638 | report_errata ERRATA_A57_813420, cortex_a57, 813420 |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 639 | report_errata ERRATA_A57_814670, cortex_a57, 814670 |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 640 | report_errata ERRATA_A57_817169, cortex_a57, 817169 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 641 | report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ |
| 642 | disable_ldnp_overread |
| 643 | report_errata ERRATA_A57_826974, cortex_a57, 826974 |
| 644 | report_errata ERRATA_A57_826977, cortex_a57, 826977 |
| 645 | report_errata ERRATA_A57_828024, cortex_a57, 828024 |
| 646 | report_errata ERRATA_A57_829520, cortex_a57, 829520 |
| 647 | report_errata ERRATA_A57_833471, cortex_a57, 833471 |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 648 | report_errata ERRATA_A57_859972, cortex_a57, 859972 |
Manish V Badarkhe | 7672edf | 2020-08-03 18:43:14 +0100 | [diff] [blame] | 649 | report_errata ERRATA_A57_1319537, cortex_a57, 1319537 |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 650 | report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 651 | report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639 |
Bipin Ravi | cf4d50a | 2022-02-15 23:24:51 -0600 | [diff] [blame] | 652 | report_errata WORKAROUND_CVE_2022_23960, cortex_a57, cve_2022_23960 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 653 | |
| 654 | ldp x8, x30, [sp], #16 |
| 655 | ret |
| 656 | endfunc cortex_a57_errata_report |
| 657 | #endif |
| 658 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 659 | /* --------------------------------------------- |
| 660 | * This function provides cortex_a57 specific |
| 661 | * register information for crash reporting. |
| 662 | * It needs to return with x6 pointing to |
| 663 | * a list of register names in ascii and |
| 664 | * x8 - x15 having values of registers to be |
| 665 | * reported. |
| 666 | * --------------------------------------------- |
| 667 | */ |
| 668 | .section .rodata.cortex_a57_regs, "aS" |
| 669 | cortex_a57_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 670 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 671 | |
| 672 | func cortex_a57_cpu_reg_dump |
| 673 | adr x6, cortex_a57_regs |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 674 | mrs x8, CORTEX_A57_ECTLR_EL1 |
| 675 | mrs x9, CORTEX_A57_MERRSR_EL1 |
| 676 | mrs x10, CORTEX_A57_L2MERRSR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 677 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 678 | endfunc cortex_a57_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 679 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 680 | declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 681 | cortex_a57_reset_func, \ |
Dimitris Papastamos | 914757c | 2018-03-12 14:47:09 +0000 | [diff] [blame] | 682 | check_errata_cve_2017_5715, \ |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 683 | CPU_NO_EXTRA2_FUNC, \ |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 684 | check_smccc_arch_workaround_3, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 685 | cortex_a57_core_pwr_dwn, \ |
| 686 | cortex_a57_cluster_pwr_dwn |