Add support for level specific cache maintenance operations
This patch adds level specific cache maintenance functions
to cache_helpers.S. The new functions 'dcsw_op_levelx',
where '1 <= x <= 3', allow to perform cache maintenance by
set/way for that particular level of cache. With this patch,
functions to support cache maintenance upto level 3 have
been implemented since it is the highest cache level for
most ARM SoCs.
These functions are now utilized in CPU specific power down
sequences to implement them as mandated by processor specific
technical reference manual.
Change-Id: Icd90ce6b51cff5a12863bcda01b93601417fd45c
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index eed1bbb..3e55297 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -134,11 +134,11 @@
bl cortex_a57_disable_l2_prefetch
/* ---------------------------------------------
- * Flush L1 cache to PoU.
+ * Flush L1 caches.
* ---------------------------------------------
*/
mov x0, #DCCISW
- bl dcsw_op_louis
+ bl dcsw_op_level1
/* ---------------------------------------------
* Come out of intra cluster coherency
@@ -168,18 +168,25 @@
*/
bl cortex_a57_disable_l2_prefetch
+ /* -------------------------------------------------
+ * Flush the L1 caches.
+ * -------------------------------------------------
+ */
+ mov x0, #DCCISW
+ bl dcsw_op_level1
+
/* ---------------------------------------------
* Disable the optional ACP.
* ---------------------------------------------
*/
bl plat_disable_acp
- /* ---------------------------------------------
- * Flush L1 and L2 caches to PoC.
- * ---------------------------------------------
+ /* -------------------------------------------------
+ * Flush the L2 caches.
+ * -------------------------------------------------
*/
mov x0, #DCCISW
- bl dcsw_op_all
+ bl dcsw_op_level2
/* ---------------------------------------------
* Come out of intra cluster coherency