Disable non-temporal hint on Cortex-A53/57
The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a significant speed degradation to any code
that employs them. The ARMv8-A architecture (see Document ARM DDI
0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint
and treat LDNP/STNP as LDP/STP instead.
This patch introduces 2 new build flags:
A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT
to enforce this behaviour on Cortex-A53 and Cortex-A57. They are
enabled by default.
The string printed in debug builds when a specific CPU errata
workaround is compiled in but skipped at runtime has been
generalised, so that it can be reused for the non-temporal hint use
case as well.
Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 05799d6..8bcb5dd 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -153,6 +153,35 @@
ret
endfunc errata_a57_813420_wa
+ /* --------------------------------------------------------------------
+ * Disable the over-read from the LDNP instruction.
+ *
+ * This applies to all revisions <= r1p2. The performance degradation
+ * observed with LDNP/STNP has been fixed on r1p3 and onwards.
+ *
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Clobbers : x0 - x5, x30
+ * ---------------------------------------------------------------------
+ */
+func a57_disable_ldnp_overread
+ /*
+ * Compare x0 against revision r1p2
+ */
+ cmp x0, #0x12
+ b.ls disable_hint
+#if DEBUG
+ b print_revision_warning
+#else
+ ret
+#endif
+disable_hint:
+ mrs x1, CPUACTLR_EL1
+ orr x1, x1, #CPUACTLR_DIS_OVERREAD
+ msr CPUACTLR_EL1, x1
+ ret
+endfunc a57_disable_ldnp_overread
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A57.
* Clobbers: x0-x5, x15, x19, x30
@@ -181,6 +210,11 @@
bl errata_a57_813420_wa
#endif
+#if A57_DISABLE_NON_TEMPORAL_HINT
+ mov x0, x15
+ bl a57_disable_ldnp_overread
+#endif
+
/* ---------------------------------------------
* As a bare minimum enable the SMP bit if it is
* not already set.