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Oliver Swede8fed2fe2019-11-11 11:11:06 +00001#
Chris Kay523e8642023-12-04 12:03:51 +00002# Copyright (c) 2021-2024, Arm Limited. All rights reserved.
Oliver Swede8fed2fe2019-11-11 11:11:06 +00003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Chris Kaye9272152021-09-28 15:52:14 +01007include common/fdt_wrappers.mk
Andre Przywaraeec45eb2020-01-24 15:02:27 +00008include lib/libfdt/libfdt.mk
9
Oliver Swede8fed2fe2019-11-11 11:11:06 +000010RESET_TO_BL31 := 1
11ifeq (${RESET_TO_BL31}, 0)
12$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
13endif
14
Oliver Swede3769b3f2019-12-16 14:08:27 +000015ifeq (${ENABLE_PIE}, 1)
16override SEPARATE_CODE_AND_RODATA := 1
17endif
18
Oliver Swede8fed2fe2019-11-11 11:11:06 +000019CTX_INCLUDE_AARCH32_REGS := 0
20ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
21$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
22endif
23
24ifeq (${TRUSTED_BOARD_BOOT}, 1)
25$(error "TRUSTED_BOARD_BOOT must be disabled")
26endif
27
Andre Przywarad9b95cc2020-07-08 13:01:00 +010028PRELOADED_BL33_BASE := 0x80080000
Oliver Swede8fed2fe2019-11-11 11:11:06 +000029
Andre Przywarad9b95cc2020-07-08 13:01:00 +010030FPGA_PRELOADED_DTB_BASE := 0x80070000
Oliver Swede8fed2fe2019-11-11 11:11:06 +000031$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
Oliver Swede8fed2fe2019-11-11 11:11:06 +000032
Andre Przywara01767932020-07-07 10:40:46 +010033FPGA_PRELOADED_CMD_LINE := 0x1000
34$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE))
35
Andre Przywara480e5942023-08-31 15:47:54 +010036ENABLE_BRBE_FOR_NS := 2
37ENABLE_TRBE_FOR_NS := 2
38ENABLE_FEAT_AMU := 2
39ENABLE_FEAT_AMUv1p1 := 2
40ENABLE_FEAT_CSV2_2 := 2
41ENABLE_FEAT_ECV := 2
42ENABLE_FEAT_FGT := 2
43ENABLE_FEAT_HCX := 2
Andre Przywara129991d2024-03-07 17:51:24 +000044ENABLE_FEAT_MTE2 := 2
45ENABLE_FEAT_TCR2 := 2
Andre Przywara480e5942023-08-31 15:47:54 +010046ENABLE_SYS_REG_TRACE_FOR_NS := 2
47ENABLE_TRF_FOR_NS := 2
Andre Przywara129991d2024-03-07 17:51:24 +000048ENABLE_SME_FOR_NS := 2
49ENABLE_SME2_FOR_NS := 2
Andre Przywara8fc8e182024-08-09 17:04:22 +010050ENABLE_FEAT_LS64_ACCDATA := 2
Tom Cosgrove2593a8a2021-08-17 08:50:53 +010051
Oliver Swede8fed2fe2019-11-11 11:11:06 +000052# Treating this as a memory-constrained port for now
53USE_COHERENT_MEM := 0
54
Oliver Swede7fbb9b52020-01-15 10:20:09 +000055# This can be overridden depending on CPU(s) used in the FPGA image
Oliver Swede8fed2fe2019-11-11 11:11:06 +000056HW_ASSISTED_COHERENCY := 1
57
Andre Przywara8b505252020-04-09 10:10:09 +010058PL011_GENERIC_UART := 1
59
Javier Almansa Sobrinoe1ecd232020-08-20 18:48:09 +010060SUPPORT_UNKNOWN_MPID ?= 1
61
Oliver Swede7fbb9b52020-01-15 10:20:09 +000062FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
63
64# select a different set of CPU files, depending on whether we compile for
65# hardware assisted coherency cores or not
66ifeq (${HW_ASSISTED_COHERENCY}, 0)
67# Cores used without DSU
68 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
69 lib/cpus/aarch64/cortex_a53.S \
70 lib/cpus/aarch64/cortex_a57.S \
71 lib/cpus/aarch64/cortex_a72.S \
72 lib/cpus/aarch64/cortex_a73.S
73else
74# AArch64-only cores
Govindraj Raja0a120912023-06-23 11:09:31 -050075 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \
Govindraj Rajaca3caf02023-06-28 08:49:21 -050076 lib/cpus/aarch64/cortex_a520.S \
Govindraj Raja0a120912023-06-23 11:09:31 -050077 lib/cpus/aarch64/cortex_a715.S \
Govindraj Raja37012fb2023-06-23 11:28:05 -050078 lib/cpus/aarch64/cortex_a720.S \
Govindraj Raja0a120912023-06-23 11:09:31 -050079 lib/cpus/aarch64/cortex_x3.S \
80 lib/cpus/aarch64/cortex_x4.S \
Daniel Boulby941a9092023-05-10 14:42:43 +010081 lib/cpus/aarch64/neoverse_n_common.S \
Govindraj Raja0a120912023-06-23 11:09:31 -050082 lib/cpus/aarch64/neoverse_n1.S \
83 lib/cpus/aarch64/neoverse_n2.S \
84 lib/cpus/aarch64/neoverse_v1.S \
Govindraj Raja106437d2024-05-17 13:35:19 -050085 lib/cpus/aarch64/cortex_a725.S \
Govindraj Raja82760142024-05-17 13:39:07 -050086 lib/cpus/aarch64/cortex_x925.S
Andre Przywaracb167672020-06-25 13:10:38 +010087
Oliver Swede7fbb9b52020-01-15 10:20:09 +000088# AArch64/AArch32 cores
89 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
90 lib/cpus/aarch64/cortex_a75.S
91endif
Oliver Swede8fed2fe2019-11-11 11:11:06 +000092
Javier Almansa Sobrinoe1ecd232020-08-20 18:48:09 +010093ifeq (${SUPPORT_UNKNOWN_MPID}, 1)
94# Add support for unknown/invalid MPIDs (aarch64 only)
95$(eval $(call add_define,SUPPORT_UNKNOWN_MPID))
96 FPGA_CPU_LIBS += lib/cpus/aarch64/generic.S
97endif
98
Andre Przywarae1cc1302020-03-25 15:50:38 +000099# Allow detection of GIC-600
100GICV3_SUPPORT_GIC600 := 1
Manish Pandeyb21cad72020-04-03 18:59:20 +0100101
Andre Przywara42ba7c92021-05-18 15:53:05 +0100102GIC_ENABLE_V4_EXTN := 1
103
Manish Pandeyb21cad72020-04-03 18:59:20 +0100104# Include GICv3 driver files
105include drivers/arm/gic/v3/gicv3.mk
106
107FPGA_GIC_SOURCES := ${GICV3_SOURCES} \
Oliver Swedeb51da812019-12-03 14:08:21 +0000108 plat/common/plat_gicv3.c \
109 plat/arm/board/arm_fpga/fpga_gicv3.c
Oliver Swede8fed2fe2019-11-11 11:11:06 +0000110
Andre Przywaraeb5cb802020-08-03 12:54:58 +0100111FDT_SOURCES := fdts/arm_fpga.dts
112
Oliver Swede8fed2fe2019-11-11 11:11:06 +0000113PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
114
115PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
116
Chris Kaye9272152021-09-28 15:52:14 +0100117BL31_SOURCES += common/fdt_fixup.c \
Andre Przywaraeec45eb2020-01-24 15:02:27 +0000118 drivers/delay_timer/delay_timer.c \
Oliver Swede8fed2fe2019-11-11 11:11:06 +0000119 drivers/delay_timer/generic_delay_timer.c \
120 drivers/arm/pl011/${ARCH}/pl011_console.S \
121 plat/common/plat_psci_common.c \
122 plat/arm/board/arm_fpga/fpga_pm.c \
123 plat/arm/board/arm_fpga/fpga_topology.c \
124 plat/arm/board/arm_fpga/fpga_console.c \
125 plat/arm/board/arm_fpga/fpga_bl31_setup.c \
126 ${FPGA_CPU_LIBS} \
127 ${FPGA_GIC_SOURCES}
128
Chris Kaye9272152021-09-28 15:52:14 +0100129BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
130
Andre Przywara45e794f2021-10-07 14:19:12 +0100131$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,bl31))
132$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/kernel_trampoline.S,bl31))
133$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,bl31))
Andre Przywara6228e432020-09-16 17:13:33 +0100134
Andrey Skvortsovcdee0962024-02-24 00:50:05 +0300135ifeq ($($(ARCH)-ld-id),gnu-gcc)
Andre Przywara64096f52024-06-14 16:09:19 +0100136 AXF_LDFLAGS += -Wl,--build-id=none -mno-fix-cortex-a53-843419
Andrey Skvortsovcdee0962024-02-24 00:50:05 +0300137else
Andre Przywara64096f52024-06-14 16:09:19 +0100138 AXF_LDFLAGS += --build-id=none
Andrey Skvortsovcdee0962024-02-24 00:50:05 +0300139endif
140
Andre Przywara64096f52024-06-14 16:09:19 +0100141AXF_LDFLAGS += -nostdlib -no-pie
142
Andre Przywara8c6d92d2021-05-14 16:13:28 +0100143bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/kernel_trampoline.o ${BUILD_PLAT}/build_axf.ld
Chris Kay1870c722024-05-02 17:52:37 +0000144 $(s)echo " LD $@"
Andre Przywara64096f52024-06-14 16:09:19 +0100145 $(q)$($(ARCH)-ld) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} ${AXF_LDFLAGS} -s -n -o ${BUILD_PLAT}/bl31.axf
Andre Przywara586de5e2020-08-03 13:06:38 +0100146
Andre Przywara6228e432020-09-16 17:13:33 +0100147all: bl31.axf