Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 1 | # |
Chris Kay | 523e864 | 2023-12-04 12:03:51 +0000 | [diff] [blame] | 2 | # Copyright (c) 2021-2024, Arm Limited. All rights reserved. |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
Chris Kay | e927215 | 2021-09-28 15:52:14 +0100 | [diff] [blame] | 7 | include common/fdt_wrappers.mk |
Andre Przywara | eec45eb | 2020-01-24 15:02:27 +0000 | [diff] [blame] | 8 | include lib/libfdt/libfdt.mk |
| 9 | |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 10 | RESET_TO_BL31 := 1 |
| 11 | ifeq (${RESET_TO_BL31}, 0) |
| 12 | $(error "This is a BL31-only port; RESET_TO_BL31 must be enabled") |
| 13 | endif |
| 14 | |
Oliver Swede | 3769b3f | 2019-12-16 14:08:27 +0000 | [diff] [blame] | 15 | ifeq (${ENABLE_PIE}, 1) |
| 16 | override SEPARATE_CODE_AND_RODATA := 1 |
| 17 | endif |
| 18 | |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 19 | CTX_INCLUDE_AARCH32_REGS := 0 |
| 20 | ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) |
| 21 | $(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") |
| 22 | endif |
| 23 | |
| 24 | ifeq (${TRUSTED_BOARD_BOOT}, 1) |
| 25 | $(error "TRUSTED_BOARD_BOOT must be disabled") |
| 26 | endif |
| 27 | |
Andre Przywara | d9b95cc | 2020-07-08 13:01:00 +0100 | [diff] [blame] | 28 | PRELOADED_BL33_BASE := 0x80080000 |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 29 | |
Andre Przywara | d9b95cc | 2020-07-08 13:01:00 +0100 | [diff] [blame] | 30 | FPGA_PRELOADED_DTB_BASE := 0x80070000 |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 31 | $(eval $(call add_define,FPGA_PRELOADED_DTB_BASE)) |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 32 | |
Andre Przywara | 0176793 | 2020-07-07 10:40:46 +0100 | [diff] [blame] | 33 | FPGA_PRELOADED_CMD_LINE := 0x1000 |
| 34 | $(eval $(call add_define,FPGA_PRELOADED_CMD_LINE)) |
| 35 | |
Andre Przywara | 480e594 | 2023-08-31 15:47:54 +0100 | [diff] [blame] | 36 | ENABLE_BRBE_FOR_NS := 2 |
| 37 | ENABLE_TRBE_FOR_NS := 2 |
| 38 | ENABLE_FEAT_AMU := 2 |
| 39 | ENABLE_FEAT_AMUv1p1 := 2 |
| 40 | ENABLE_FEAT_CSV2_2 := 2 |
| 41 | ENABLE_FEAT_ECV := 2 |
| 42 | ENABLE_FEAT_FGT := 2 |
| 43 | ENABLE_FEAT_HCX := 2 |
Andre Przywara | 480e594 | 2023-08-31 15:47:54 +0100 | [diff] [blame] | 44 | ENABLE_SYS_REG_TRACE_FOR_NS := 2 |
| 45 | ENABLE_TRF_FOR_NS := 2 |
Tom Cosgrove | 2593a8a | 2021-08-17 08:50:53 +0100 | [diff] [blame] | 46 | |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 47 | # Treating this as a memory-constrained port for now |
| 48 | USE_COHERENT_MEM := 0 |
| 49 | |
Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 50 | # This can be overridden depending on CPU(s) used in the FPGA image |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 51 | HW_ASSISTED_COHERENCY := 1 |
| 52 | |
Andre Przywara | 8b50525 | 2020-04-09 10:10:09 +0100 | [diff] [blame] | 53 | PL011_GENERIC_UART := 1 |
| 54 | |
Javier Almansa Sobrino | e1ecd23 | 2020-08-20 18:48:09 +0100 | [diff] [blame] | 55 | SUPPORT_UNKNOWN_MPID ?= 1 |
| 56 | |
Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 57 | FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S |
| 58 | |
| 59 | # select a different set of CPU files, depending on whether we compile for |
| 60 | # hardware assisted coherency cores or not |
| 61 | ifeq (${HW_ASSISTED_COHERENCY}, 0) |
| 62 | # Cores used without DSU |
| 63 | FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ |
| 64 | lib/cpus/aarch64/cortex_a53.S \ |
| 65 | lib/cpus/aarch64/cortex_a57.S \ |
| 66 | lib/cpus/aarch64/cortex_a72.S \ |
| 67 | lib/cpus/aarch64/cortex_a73.S |
| 68 | else |
| 69 | # AArch64-only cores |
Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 70 | FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \ |
Govindraj Raja | ca3caf0 | 2023-06-28 08:49:21 -0500 | [diff] [blame] | 71 | lib/cpus/aarch64/cortex_a520.S \ |
Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 72 | lib/cpus/aarch64/cortex_a715.S \ |
Govindraj Raja | 37012fb | 2023-06-23 11:28:05 -0500 | [diff] [blame] | 73 | lib/cpus/aarch64/cortex_a720.S \ |
Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 74 | lib/cpus/aarch64/cortex_x3.S \ |
| 75 | lib/cpus/aarch64/cortex_x4.S \ |
Daniel Boulby | 941a909 | 2023-05-10 14:42:43 +0100 | [diff] [blame] | 76 | lib/cpus/aarch64/neoverse_n_common.S \ |
Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 77 | lib/cpus/aarch64/neoverse_n1.S \ |
| 78 | lib/cpus/aarch64/neoverse_n2.S \ |
| 79 | lib/cpus/aarch64/neoverse_v1.S \ |
Govindraj Raja | 0a12091 | 2023-06-23 11:09:31 -0500 | [diff] [blame] | 80 | lib/cpus/aarch64/cortex_chaberton.S \ |
Daniel Boulby | 941a909 | 2023-05-10 14:42:43 +0100 | [diff] [blame] | 81 | lib/cpus/aarch64/cortex_blackhawk.S |
Andre Przywara | cb16767 | 2020-06-25 13:10:38 +0100 | [diff] [blame] | 82 | |
Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 83 | # AArch64/AArch32 cores |
| 84 | FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ |
| 85 | lib/cpus/aarch64/cortex_a75.S |
| 86 | endif |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 87 | |
Javier Almansa Sobrino | e1ecd23 | 2020-08-20 18:48:09 +0100 | [diff] [blame] | 88 | ifeq (${SUPPORT_UNKNOWN_MPID}, 1) |
| 89 | # Add support for unknown/invalid MPIDs (aarch64 only) |
| 90 | $(eval $(call add_define,SUPPORT_UNKNOWN_MPID)) |
| 91 | FPGA_CPU_LIBS += lib/cpus/aarch64/generic.S |
| 92 | endif |
| 93 | |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 94 | # Allow detection of GIC-600 |
| 95 | GICV3_SUPPORT_GIC600 := 1 |
Manish Pandey | b21cad7 | 2020-04-03 18:59:20 +0100 | [diff] [blame] | 96 | |
Andre Przywara | 42ba7c9 | 2021-05-18 15:53:05 +0100 | [diff] [blame] | 97 | GIC_ENABLE_V4_EXTN := 1 |
| 98 | |
Manish Pandey | b21cad7 | 2020-04-03 18:59:20 +0100 | [diff] [blame] | 99 | # Include GICv3 driver files |
| 100 | include drivers/arm/gic/v3/gicv3.mk |
| 101 | |
| 102 | FPGA_GIC_SOURCES := ${GICV3_SOURCES} \ |
Oliver Swede | b51da81 | 2019-12-03 14:08:21 +0000 | [diff] [blame] | 103 | plat/common/plat_gicv3.c \ |
| 104 | plat/arm/board/arm_fpga/fpga_gicv3.c |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 105 | |
Andre Przywara | eb5cb80 | 2020-08-03 12:54:58 +0100 | [diff] [blame] | 106 | FDT_SOURCES := fdts/arm_fpga.dts |
| 107 | |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 108 | PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include |
| 109 | |
| 110 | PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S |
| 111 | |
Chris Kay | e927215 | 2021-09-28 15:52:14 +0100 | [diff] [blame] | 112 | BL31_SOURCES += common/fdt_fixup.c \ |
Andre Przywara | eec45eb | 2020-01-24 15:02:27 +0000 | [diff] [blame] | 113 | drivers/delay_timer/delay_timer.c \ |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 114 | drivers/delay_timer/generic_delay_timer.c \ |
| 115 | drivers/arm/pl011/${ARCH}/pl011_console.S \ |
| 116 | plat/common/plat_psci_common.c \ |
| 117 | plat/arm/board/arm_fpga/fpga_pm.c \ |
| 118 | plat/arm/board/arm_fpga/fpga_topology.c \ |
| 119 | plat/arm/board/arm_fpga/fpga_console.c \ |
| 120 | plat/arm/board/arm_fpga/fpga_bl31_setup.c \ |
| 121 | ${FPGA_CPU_LIBS} \ |
| 122 | ${FPGA_GIC_SOURCES} |
| 123 | |
Chris Kay | e927215 | 2021-09-28 15:52:14 +0100 | [diff] [blame] | 124 | BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} |
| 125 | |
Andre Przywara | 45e794f | 2021-10-07 14:19:12 +0100 | [diff] [blame] | 126 | $(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,bl31)) |
| 127 | $(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/kernel_trampoline.S,bl31)) |
| 128 | $(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,bl31)) |
Andre Przywara | 6228e43 | 2020-09-16 17:13:33 +0100 | [diff] [blame] | 129 | |
Andrey Skvortsov | cdee096 | 2024-02-24 00:50:05 +0300 | [diff] [blame^] | 130 | ifeq ($($(ARCH)-ld-id),gnu-gcc) |
| 131 | PLAT_LDFLAGS += -Wl,--strip-debug |
| 132 | else |
| 133 | PLAT_LDFLAGS += --strip-debug |
| 134 | endif |
| 135 | |
Andre Przywara | 8c6d92d | 2021-05-14 16:13:28 +0100 | [diff] [blame] | 136 | bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/kernel_trampoline.o ${BUILD_PLAT}/build_axf.ld |
Andre Przywara | 6228e43 | 2020-09-16 17:13:33 +0100 | [diff] [blame] | 137 | $(ECHO) " LD $@" |
Andrey Skvortsov | cdee096 | 2024-02-24 00:50:05 +0300 | [diff] [blame^] | 138 | $(Q)$($(ARCH)-ld) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} $(TF_LDFLAGS) $(PLAT_LDFLAGS) -s -n -o ${BUILD_PLAT}/bl31.axf |
Andre Przywara | 586de5e | 2020-08-03 13:06:38 +0100 | [diff] [blame] | 139 | |
Andre Przywara | 6228e43 | 2020-09-16 17:13:33 +0100 | [diff] [blame] | 140 | all: bl31.axf |