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Nishanth Menon0192f892016-10-14 01:13:34 +00001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <string.h>
9
10#include <platform_def.h>
11
Nishanth Menon0192f892016-10-14 01:13:34 +000012#include <arch.h>
13#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <common/bl_common.h>
15#include <common/debug.h>
Nishanth Menon651ff1a2020-12-10 20:51:51 -060016#include <lib/mmio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/xlat_tables/xlat_tables_v2.h>
18
Nishanth Menonce976042016-10-14 01:13:44 +000019#include <k3_console.h>
Nishanth Menonf97ad372016-10-14 01:13:49 +000020#include <k3_gicv3.h>
Andrew F. Davisa513b2a2018-05-04 19:06:09 +000021#include <ti_sci.h>
Nishanth Menon0192f892016-10-14 01:13:34 +000022
Andrew Davis525c0b22023-10-25 16:42:27 -050023#define ADDR_DOWN(_adr) (_adr & XLAT_ADDR_MASK(2U))
24#define SIZE_UP(_adr, _sz) (round_up((_adr + _sz), XLAT_BLOCK_SIZE(2U)) - ADDR_DOWN(_adr))
25
26#define K3_MAP_REGION_FLAT(_adr, _sz, _attr) \
27 MAP_REGION_FLAT(ADDR_DOWN(_adr), SIZE_UP(_adr, _sz), _attr)
28
Nishanth Menon3ed1b282016-10-14 01:13:45 +000029/* Table of regions to map using the MMU */
Andrew F. Davis02de6d92018-10-29 10:41:28 -050030const mmap_region_t plat_k3_mmap[] = {
Andrew Davis525c0b22023-10-25 16:42:27 -050031 K3_MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
32 K3_MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
33 K3_MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
34 K3_MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
35 K3_MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
36 K3_MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
Nishanth Menon3ed1b282016-10-14 01:13:45 +000037 { /* sentinel */ }
38};
39
Benjamin Faire62e5772016-10-14 01:13:52 +000040/*
41 * Placeholder variables for maintaining information about the next image(s)
42 */
43static entry_point_info_t bl32_image_ep_info;
44static entry_point_info_t bl33_image_ep_info;
45
46/*******************************************************************************
47 * Gets SPSR for BL33 entry
48 ******************************************************************************/
49static uint32_t k3_get_spsr_for_bl33_entry(void)
50{
51 unsigned long el_status;
52 unsigned int mode;
53 uint32_t spsr;
54
55 /* Figure out what mode we enter the non-secure world in */
56 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
57 el_status &= ID_AA64PFR0_ELX_MASK;
58
59 mode = (el_status) ? MODE_EL2 : MODE_EL1;
60
61 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
62 return spsr;
63}
64
Nishanth Menon0192f892016-10-14 01:13:34 +000065/*******************************************************************************
66 * Perform any BL3-1 early platform setup, such as console init and deciding on
67 * memory layout.
68 ******************************************************************************/
Antonio Nino Diaz27187bc2018-09-24 17:16:45 +010069void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
70 u_register_t arg2, u_register_t arg3)
Nishanth Menon0192f892016-10-14 01:13:34 +000071{
Andrew Davisb9104702022-11-15 18:04:41 -060072 /* Initialize the console to provide early debug support */
73 k3_console_setup();
Nishanth Menonce976042016-10-14 01:13:44 +000074
Benjamin Faire62e5772016-10-14 01:13:52 +000075#ifdef BL32_BASE
76 /* Populate entry point information for BL32 */
77 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
78 bl32_image_ep_info.pc = BL32_BASE;
79 bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
80 DISABLE_ALL_EXCEPTIONS);
81 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
82#endif
83
84 /* Populate entry point information for BL33 */
85 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
86 bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
87 bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry();
88 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
89
90#ifdef K3_HW_CONFIG_BASE
91 /*
92 * According to the file ``Documentation/arm64/booting.txt`` of the
93 * Linux kernel tree, Linux expects the physical address of the device
94 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
95 * must be 0.
96 */
97 bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE;
98 bl33_image_ep_info.args.arg1 = 0U;
99 bl33_image_ep_info.args.arg2 = 0U;
100 bl33_image_ep_info.args.arg3 = 0U;
101#endif
Nishanth Menon0192f892016-10-14 01:13:34 +0000102}
103
Nishanth Menon0192f892016-10-14 01:13:34 +0000104void bl31_plat_arch_setup(void)
105{
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100106 const mmap_region_t bl_regions[] = {
Nishanth Menond15f46e2021-03-26 00:34:17 -0500107 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE),
Andrew F. Davis3a310882019-04-25 13:54:09 -0400108 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE),
109 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_RO | MT_SECURE),
110#if USE_COHERENT_MEM
111 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE),
112#endif
Andrew F. Daviscab6fa62019-01-22 14:25:08 -0600113 { /* sentinel */ }
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100114 };
115
Andrew F. Davis02de6d92018-10-29 10:41:28 -0500116 setup_page_tables(bl_regions, plat_k3_mmap);
Nishanth Menon3ed1b282016-10-14 01:13:45 +0000117 enable_mmu_el3(0);
Nishanth Menon0192f892016-10-14 01:13:34 +0000118}
119
120void bl31_platform_setup(void)
121{
Andrew F. Davis75ad53f2019-01-22 12:39:31 -0600122 k3_gic_driver_init(K3_GIC_BASE);
Nishanth Menonf97ad372016-10-14 01:13:49 +0000123 k3_gic_init();
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000124
125 ti_sci_init();
Nishanth Menon0192f892016-10-14 01:13:34 +0000126}
127
128void platform_mem_init(void)
129{
130 /* Do nothing for now... */
131}
132
Nishanth Menon1f0b51b2016-10-14 01:13:48 +0000133unsigned int plat_get_syscnt_freq2(void)
134{
Nishanth Menon651ff1a2020-12-10 20:51:51 -0600135 uint32_t gtc_freq;
136 uint32_t gtc_ctrl;
137
138 /* Lets try and provide basic diagnostics - cost is low */
139 gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET);
140 /* Did the bootloader fail to enable timer and OS guys are confused? */
141 if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) {
142 ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n");
143 }
144 /*
145 * If debug will not pause time, we will have issues like
146 * drivers timing out while debugging, in cases of OS like Linux,
147 * RCU stall errors, which can be hard to differentiate vs real issues.
148 */
149 if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) {
150 WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n");
151 }
152
153 gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET);
154 /* Many older bootloaders may have missed programming FID0 register */
155 if (gtc_freq != 0U) {
156 return gtc_freq;
157 }
158
159 /*
160 * We could have just warned about this, but this can have serious
161 * hard to debug side effects if we are NOT sure what the actual
162 * frequency is. Lets make sure people don't miss this.
163 */
164 ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n",
165 SYS_COUNTER_FREQ_IN_TICKS);
166
Nishanth Menon1f0b51b2016-10-14 01:13:48 +0000167 return SYS_COUNTER_FREQ_IN_TICKS;
168}
169
Nishanth Menon0192f892016-10-14 01:13:34 +0000170/*******************************************************************************
171 * Return a pointer to the 'entry_point_info' structure of the next image
172 * for the security state specified. BL3-3 corresponds to the non-secure
173 * image type while BL3-2 corresponds to the secure image type. A NULL
174 * pointer is returned if the image does not exist.
175 ******************************************************************************/
176entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
177{
Benjamin Faire62e5772016-10-14 01:13:52 +0000178 entry_point_info_t *next_image_info;
179
180 assert(sec_state_is_valid(type));
181 next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info :
182 &bl32_image_ep_info;
183 /*
184 * None of the images on the ARM development platforms can have 0x0
185 * as the entrypoint
186 */
187 if (next_image_info->pc)
188 return next_image_info;
189
190 NOTICE("Requested nonexistent image\n");
Nishanth Menon0192f892016-10-14 01:13:34 +0000191 return NULL;
192}