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Nishanth Menon0192f892016-10-14 01:13:34 +00001/*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <string.h>
9
10#include <platform_def.h>
11
Nishanth Menon0192f892016-10-14 01:13:34 +000012#include <arch.h>
13#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <common/bl_common.h>
15#include <common/debug.h>
Nishanth Menon651ff1a2020-12-10 20:51:51 -060016#include <lib/mmio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/xlat_tables/xlat_tables_v2.h>
18
Nishanth Menonce976042016-10-14 01:13:44 +000019#include <k3_console.h>
Nishanth Menonf97ad372016-10-14 01:13:49 +000020#include <k3_gicv3.h>
Andrew F. Davisa513b2a2018-05-04 19:06:09 +000021#include <ti_sci.h>
Nishanth Menon0192f892016-10-14 01:13:34 +000022
Nishanth Menon3ed1b282016-10-14 01:13:45 +000023/* Table of regions to map using the MMU */
Andrew F. Davis02de6d92018-10-29 10:41:28 -050024const mmap_region_t plat_k3_mmap[] = {
Andrew F. Daviscab6fa62019-01-22 14:25:08 -060025 MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
26 MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
Nishanth Menon651ff1a2020-12-10 20:51:51 -060027 MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
Andrew F. Daviscab6fa62019-01-22 14:25:08 -060028 MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
Andrew F. Davis537d3ff2018-05-04 19:06:08 +000029 MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
30 MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
Nishanth Menon3ed1b282016-10-14 01:13:45 +000031 { /* sentinel */ }
32};
33
Benjamin Faire62e5772016-10-14 01:13:52 +000034/*
35 * Placeholder variables for maintaining information about the next image(s)
36 */
37static entry_point_info_t bl32_image_ep_info;
38static entry_point_info_t bl33_image_ep_info;
39
40/*******************************************************************************
41 * Gets SPSR for BL33 entry
42 ******************************************************************************/
43static uint32_t k3_get_spsr_for_bl33_entry(void)
44{
45 unsigned long el_status;
46 unsigned int mode;
47 uint32_t spsr;
48
49 /* Figure out what mode we enter the non-secure world in */
50 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
51 el_status &= ID_AA64PFR0_ELX_MASK;
52
53 mode = (el_status) ? MODE_EL2 : MODE_EL1;
54
55 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
56 return spsr;
57}
58
Nishanth Menon0192f892016-10-14 01:13:34 +000059/*******************************************************************************
60 * Perform any BL3-1 early platform setup, such as console init and deciding on
61 * memory layout.
62 ******************************************************************************/
Antonio Nino Diaz27187bc2018-09-24 17:16:45 +010063void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
64 u_register_t arg2, u_register_t arg3)
Nishanth Menon0192f892016-10-14 01:13:34 +000065{
66 /* There are no parameters from BL2 if BL31 is a reset vector */
Antonio Nino Diaz27187bc2018-09-24 17:16:45 +010067 assert(arg0 == 0U);
68 assert(arg1 == 0U);
Benjamin Faire62e5772016-10-14 01:13:52 +000069
Andrew Davisb9104702022-11-15 18:04:41 -060070 /* Initialize the console to provide early debug support */
71 k3_console_setup();
Nishanth Menonce976042016-10-14 01:13:44 +000072
Benjamin Faire62e5772016-10-14 01:13:52 +000073#ifdef BL32_BASE
74 /* Populate entry point information for BL32 */
75 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
76 bl32_image_ep_info.pc = BL32_BASE;
77 bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
78 DISABLE_ALL_EXCEPTIONS);
79 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
80#endif
81
82 /* Populate entry point information for BL33 */
83 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
84 bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
85 bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry();
86 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
87
88#ifdef K3_HW_CONFIG_BASE
89 /*
90 * According to the file ``Documentation/arm64/booting.txt`` of the
91 * Linux kernel tree, Linux expects the physical address of the device
92 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
93 * must be 0.
94 */
95 bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE;
96 bl33_image_ep_info.args.arg1 = 0U;
97 bl33_image_ep_info.args.arg2 = 0U;
98 bl33_image_ep_info.args.arg3 = 0U;
99#endif
Nishanth Menon0192f892016-10-14 01:13:34 +0000100}
101
Nishanth Menon0192f892016-10-14 01:13:34 +0000102void bl31_plat_arch_setup(void)
103{
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100104 const mmap_region_t bl_regions[] = {
Nishanth Menond15f46e2021-03-26 00:34:17 -0500105 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE),
Andrew F. Davis3a310882019-04-25 13:54:09 -0400106 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE),
107 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_RO | MT_SECURE),
108#if USE_COHERENT_MEM
109 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE),
110#endif
Andrew F. Daviscab6fa62019-01-22 14:25:08 -0600111 { /* sentinel */ }
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100112 };
113
Andrew F. Davis02de6d92018-10-29 10:41:28 -0500114 setup_page_tables(bl_regions, plat_k3_mmap);
Nishanth Menon3ed1b282016-10-14 01:13:45 +0000115 enable_mmu_el3(0);
Nishanth Menon0192f892016-10-14 01:13:34 +0000116}
117
118void bl31_platform_setup(void)
119{
Andrew F. Davis75ad53f2019-01-22 12:39:31 -0600120 k3_gic_driver_init(K3_GIC_BASE);
Nishanth Menonf97ad372016-10-14 01:13:49 +0000121 k3_gic_init();
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000122
123 ti_sci_init();
Andrew Davisfbc99cf2022-11-15 18:08:16 -0600124
125 if (ti_sci_device_get(PLAT_BOARD_DEVICE_ID)) {
126 WARN("Unable to take system power reference\n");
127 }
Nishanth Menon0192f892016-10-14 01:13:34 +0000128}
129
130void platform_mem_init(void)
131{
132 /* Do nothing for now... */
133}
134
Nishanth Menon1f0b51b2016-10-14 01:13:48 +0000135unsigned int plat_get_syscnt_freq2(void)
136{
Nishanth Menon651ff1a2020-12-10 20:51:51 -0600137 uint32_t gtc_freq;
138 uint32_t gtc_ctrl;
139
140 /* Lets try and provide basic diagnostics - cost is low */
141 gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET);
142 /* Did the bootloader fail to enable timer and OS guys are confused? */
143 if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) {
144 ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n");
145 }
146 /*
147 * If debug will not pause time, we will have issues like
148 * drivers timing out while debugging, in cases of OS like Linux,
149 * RCU stall errors, which can be hard to differentiate vs real issues.
150 */
151 if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) {
152 WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n");
153 }
154
155 gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET);
156 /* Many older bootloaders may have missed programming FID0 register */
157 if (gtc_freq != 0U) {
158 return gtc_freq;
159 }
160
161 /*
162 * We could have just warned about this, but this can have serious
163 * hard to debug side effects if we are NOT sure what the actual
164 * frequency is. Lets make sure people don't miss this.
165 */
166 ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n",
167 SYS_COUNTER_FREQ_IN_TICKS);
168
Nishanth Menon1f0b51b2016-10-14 01:13:48 +0000169 return SYS_COUNTER_FREQ_IN_TICKS;
170}
171
Nishanth Menon0192f892016-10-14 01:13:34 +0000172/*******************************************************************************
173 * Return a pointer to the 'entry_point_info' structure of the next image
174 * for the security state specified. BL3-3 corresponds to the non-secure
175 * image type while BL3-2 corresponds to the secure image type. A NULL
176 * pointer is returned if the image does not exist.
177 ******************************************************************************/
178entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
179{
Benjamin Faire62e5772016-10-14 01:13:52 +0000180 entry_point_info_t *next_image_info;
181
182 assert(sec_state_is_valid(type));
183 next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info :
184 &bl32_image_ep_info;
185 /*
186 * None of the images on the ARM development platforms can have 0x0
187 * as the entrypoint
188 */
189 if (next_image_info->pc)
190 return next_image_info;
191
192 NOTICE("Requested nonexistent image\n");
Nishanth Menon0192f892016-10-14 01:13:34 +0000193 return NULL;
194}