Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 1 | /* |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __CORTEX_A72_H__ |
| 8 | #define __CORTEX_A72_H__ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 9 | #include <utils_def.h> |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 10 | |
| 11 | /* Cortex-A72 midr for revision 0 */ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 12 | #define CORTEX_A72_MIDR 0x410FD080 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 13 | |
| 14 | /******************************************************************************* |
| 15 | * CPU Extended Control register specific definitions. |
| 16 | ******************************************************************************/ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 17 | #define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 18 | |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 19 | #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) |
| 20 | #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) |
| 21 | #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) |
| 22 | #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 23 | |
| 24 | /******************************************************************************* |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 25 | * CPU Memory Error Syndrome register specific definitions. |
| 26 | ******************************************************************************/ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 27 | #define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 28 | |
| 29 | /******************************************************************************* |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 30 | * CPU Auxiliary Control register specific definitions. |
| 31 | ******************************************************************************/ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 32 | #define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 33 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 34 | #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) |
| 35 | #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) |
| 36 | #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 37 | #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 38 | |
| 39 | /******************************************************************************* |
| 40 | * L2 Control register specific definitions. |
| 41 | ******************************************************************************/ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 42 | #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 43 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 44 | #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 45 | #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 46 | |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 47 | #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 |
| 48 | #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 |
| 49 | #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 50 | |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 51 | /******************************************************************************* |
| 52 | * L2 Memory Error Syndrome register specific definitions. |
| 53 | ******************************************************************************/ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 54 | #define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 55 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 56 | #if !ERROR_DEPRECATED |
| 57 | /* |
| 58 | * These registers were previously wrongly named. Provide previous definitions so |
| 59 | * as not to break platforms that continue using them. |
| 60 | */ |
| 61 | #define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR_EL1 |
| 62 | |
| 63 | #define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH |
| 64 | #define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA |
| 65 | #define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI |
| 66 | #endif /* !ERROR_DEPRECATED */ |
| 67 | |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 68 | #endif /* __CORTEX_A72_H__ */ |