Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.
NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index 51f7de6..90f0abd 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,42 +13,42 @@
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
-#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
+#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
-#define CPUECTLR_SMP_BIT (1 << 6)
-#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
-#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
-#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
+#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
+#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
+#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
+#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
-#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */
+#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */
+#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0
-#define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
-#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
-#define CPUACTLR_DCC_AS_DCCI (1 << 44)
+#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
+#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
+#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
-#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */
+#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
-#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0
-#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6
+#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
+#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
-#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
-#define L2_TAG_RAM_LATENCY_2_CYCLES 0x1
-#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
+#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
-#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
+#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
#endif /* __CORTEX_A72_H__ */