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Varun Wadekarecd6a5a2018-04-09 17:48:58 -07001/*
Varun Wadekar2909fa32020-01-09 08:52:10 -08002 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Varun Wadekar2909fa32020-01-09 08:52:10 -08007#ifndef TEGRA_DEF_H
8#define TEGRA_DEF_H
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07009
10#include <lib/utils_def.h>
11
12/*******************************************************************************
Steven Kao0e6dce62018-02-09 21:01:49 +080013 * Chip specific page table and MMU setup constants
14 ******************************************************************************/
15#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
16#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40)
17
18/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070019 * These values are used by the PSCI implementation during the `CPU_SUSPEND`
20 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
21 * parameter.
22 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080023#define PSTATE_ID_CORE_IDLE U(6)
24#define PSTATE_ID_CORE_POWERDN U(7)
25#define PSTATE_ID_SOC_POWERDN U(2)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070026
27/*******************************************************************************
28 * Platform power states (used by PSCI framework)
29 *
30 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
31 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
32 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080033#define PLAT_MAX_RET_STATE U(1)
34#define PLAT_MAX_OFF_STATE U(8)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070035
36/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070037 * Secure IRQ definitions
38 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -080039#define TEGRA194_MAX_SEC_IRQS U(2)
40#define TEGRA194_TOP_WDT_IRQ U(49)
41#define TEGRA194_AON_WDT_IRQ U(50)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070042
Varun Wadekar362a6b22017-11-10 11:04:42 -080043#define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070044
45/*******************************************************************************
46 * Tegra Miscellanous register constants
47 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080048#define TEGRA_MISC_BASE U(0x00100000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070049
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080050#define HARDWARE_REVISION_OFFSET U(0x4)
51#define MISCREG_EMU_REVID U(0x3160)
52#define BOARD_MASK_BITS U(0xFF)
53#define BOARD_SHIFT_BITS U(24)
54#define MISCREG_PFCFG U(0x200C)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070055
56/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070057 * Tegra Memory Controller constants
58 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080059#define TEGRA_MC_STREAMID_BASE U(0x02C00000)
60#define TEGRA_MC_BASE U(0x02C10000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070061
Varun Wadekar07897a92017-02-13 09:00:04 -080062/* General Security Carveout register macros */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080063#define MC_GSC_CONFIG_REGS_SIZE U(0x40)
64#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
65#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0)
66#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
67#define MC_GSC_BASE_LO_SHIFT U(12)
68#define MC_GSC_BASE_LO_MASK U(0xFFFFF)
69#define MC_GSC_BASE_HI_SHIFT U(0)
70#define MC_GSC_BASE_HI_MASK U(3)
Varun Wadekar4309d7b2017-10-03 15:25:44 -070071#define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31)
Varun Wadekar07897a92017-02-13 09:00:04 -080072
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070073/* TZDRAM carveout configuration registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080074#define MC_SECURITY_CFG0_0 U(0x70)
75#define MC_SECURITY_CFG1_0 U(0x74)
76#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070077
Harvey Hsieh53fc0322017-08-09 16:26:33 +080078#define MC_SECURITY_BOM_MASK (U(0xFFF) << 20)
79#define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0)
80#define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0)
81
Steven Kaoee93ed12017-11-14 19:12:58 +080082#define MC_SECURITY_CFG_REG_CTRL_0 U(0x154)
83#define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0)
Steven Kaob2b43052017-11-30 11:53:29 +080084#define SECURITY_CFG_WRITE_ACCESS_ENABLE U(0x0)
85#define SECURITY_CFG_WRITE_ACCESS_DISABLE U(0x1)
Steven Kaoee93ed12017-11-14 19:12:58 +080086
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070087/* Video Memory carveout configuration registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080088#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
89#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
90#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070091
Varun Wadekar07897a92017-02-13 09:00:04 -080092/*
93 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
94 * non-overlapping Video memory region
95 */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080096#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
97#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
98#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
99#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
100#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
Varun Wadekar07897a92017-02-13 09:00:04 -0800101
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700102/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800103#define MC_TZRAM_CARVEOUT_CFG U(0x2190)
104#define MC_TZRAM_BASE_LO U(0x2194)
105#define MC_TZRAM_BASE_HI U(0x2198)
106#define MC_TZRAM_SIZE U(0x219C)
Varun Wadekar4309d7b2017-10-03 15:25:44 -0700107#define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0)
108#define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4)
109#define TZRAM_ALLOW_MPCORER (U(1) << 7)
110#define TZRAM_ALLOW_MPCOREW (U(1) << 25)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700111
112/* Memory Controller Reset Control registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800113#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28)
114#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29)
115#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30)
116#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700117
118/*******************************************************************************
119 * Tegra UART Controller constants
120 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800121#define TEGRA_UARTA_BASE U(0x03100000)
122#define TEGRA_UARTB_BASE U(0x03110000)
123#define TEGRA_UARTC_BASE U(0x0C280000)
124#define TEGRA_UARTD_BASE U(0x03130000)
125#define TEGRA_UARTE_BASE U(0x03140000)
126#define TEGRA_UARTF_BASE U(0x03150000)
127#define TEGRA_UARTG_BASE U(0x0C290000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700128
129/*******************************************************************************
130 * Tegra Fuse Controller related constants
131 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800132#define TEGRA_FUSE_BASE U(0x03820000)
133#define OPT_SUBREVISION U(0x248)
134#define SUBREVISION_MASK U(0xF)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700135
136/*******************************************************************************
137 * GICv2 & interrupt handling related constants
138 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800139#define TEGRA_GICD_BASE U(0x03881000)
140#define TEGRA_GICC_BASE U(0x03882000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700141
142/*******************************************************************************
143 * Security Engine related constants
144 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800145#define TEGRA_SE0_BASE U(0x03AC0000)
Steven Kao530b2172017-06-23 16:18:58 +0800146#define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
147#define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC)
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800148#define TEGRA_PKA1_BASE U(0x03AD0000)
Steven Kao530b2172017-06-23 16:18:58 +0800149#define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144)
150#define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800151#define TEGRA_RNG1_BASE U(0x03AE0000)
Steven Kao530b2172017-06-23 16:18:58 +0800152#define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700153
154/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700155 * Tegra hardware synchronization primitives for the SPE engine
156 ******************************************************************************/
157#define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000)
158#define TEGRA_CONSOLE_SPE_BASE (TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000))
159
160/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700161 * Tegra micro-seconds timer constants
162 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800163#define TEGRA_TMRUS_BASE U(0x0C2E0000)
164#define TEGRA_TMRUS_SIZE U(0x10000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700165
166/*******************************************************************************
167 * Tegra Power Mgmt Controller constants
168 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800169#define TEGRA_PMC_BASE U(0x0C360000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700170
171/*******************************************************************************
172 * Tegra scratch registers constants
173 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800174#define TEGRA_SCRATCH_BASE U(0x0C390000)
steven kao150d0332017-12-23 17:58:58 -0800175#define SECURE_SCRATCH_RSV81_LO U(0x2EC)
176#define SECURE_SCRATCH_RSV81_HI U(0x2F0)
Steven Kao4607f172017-10-23 18:35:14 +0800177#define SECURE_SCRATCH_RSV97 U(0x36C)
178#define SECURE_SCRATCH_RSV99_LO U(0x37C)
179#define SECURE_SCRATCH_RSV99_HI U(0x380)
180#define SECURE_SCRATCH_RSV109_LO U(0x3CC)
181#define SECURE_SCRATCH_RSV109_HI U(0x3D0)
182
steven kao150d0332017-12-23 17:58:58 -0800183#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV81_LO
184#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV81_HI
Steven Kao4607f172017-10-23 18:35:14 +0800185#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97
186#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO
187#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI
188#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO
189#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700190
191/*******************************************************************************
192 * Tegra Memory Mapped Control Register Access Bus constants
193 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800194#define TEGRA_MMCRAB_BASE U(0x0E000000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700195
196/*******************************************************************************
197 * Tegra SMMU Controller constants
198 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800199#define TEGRA_SMMU0_BASE U(0x12000000)
200#define TEGRA_SMMU1_BASE U(0x11000000)
201#define TEGRA_SMMU2_BASE U(0x10000000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700202
203/*******************************************************************************
204 * Tegra TZRAM constants
205 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800206#define TEGRA_TZRAM_BASE U(0x40000000)
207#define TEGRA_TZRAM_SIZE U(0x40000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700208
209/*******************************************************************************
210 * Tegra Clock and Reset Controller constants
211 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800212#define TEGRA_CAR_RESET_BASE U(0x20000000)
Jeetesh Burman0f174f12018-01-22 16:52:11 +0530213#define TEGRA_GPU_RESET_REG_OFFSET U(0x18)
214#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C)
215#define GPU_RESET_BIT (U(1) << 0)
216#define GPU_SET_BIT (U(1) << 0)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700217
Varun Wadekar00759902017-05-31 11:41:00 -0700218/*******************************************************************************
Ajay Gupta81621092017-08-01 15:53:04 -0700219 * XUSB PADCTL
220 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800221#define TEGRA_XUSB_PADCTL_BASE U(0x3520000)
222#define TEGRA_XUSB_PADCTL_SIZE U(0x10000)
223#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c)
224#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370)
225#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374)
226#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378)
227#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c)
228#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c)
Ajay Gupta81621092017-08-01 15:53:04 -0700229
230/*******************************************************************************
231 * XUSB STREAMIDs
232 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800233#define TEGRA_SID_XUSB_HOST U(0x1b)
234#define TEGRA_SID_XUSB_DEV U(0x1c)
235#define TEGRA_SID_XUSB_VF0 U(0x5d)
236#define TEGRA_SID_XUSB_VF1 U(0x5e)
237#define TEGRA_SID_XUSB_VF2 U(0x5f)
238#define TEGRA_SID_XUSB_VF3 U(0x60)
Ajay Gupta81621092017-08-01 15:53:04 -0700239
Varun Wadekar2909fa32020-01-09 08:52:10 -0800240#endif /* TEGRA_DEF_H */