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Achin Gupta7aea9082014-02-01 07:51:28 +00001/*
Zelalem Aweke42401112022-01-05 17:12:24 -06002 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
Achin Gupta7aea9082014-02-01 07:51:28 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7aea9082014-02-01 07:51:28 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <stdbool.h>
9#include <string.h>
10
11#include <platform_def.h>
12
Achin Gupta27b895e2014-05-04 18:38:28 +010013#include <arch.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000014#include <arch_helpers.h>
Soby Mathew830f0ad2019-07-12 09:23:38 +010015#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <bl31/interrupt_mgmt.h>
17#include <common/bl_common.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010018#include <context.h>
Zelalem Awekef92c0cb2022-01-31 16:59:42 -060019#include <drivers/arm/gicv3.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <lib/el3_runtime/context_mgmt.h>
21#include <lib/el3_runtime/pubsub_events.h>
22#include <lib/extensions/amu.h>
23#include <lib/extensions/mpam.h>
johpow019baade32021-07-08 14:14:00 -050024#include <lib/extensions/sme.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000025#include <lib/extensions/spe.h>
26#include <lib/extensions/sve.h>
Manish V Badarkhef356f7e2021-06-29 11:44:20 +010027#include <lib/extensions/sys_reg_trace.h>
Manish V Badarkhe20df29c2021-07-02 09:10:56 +010028#include <lib/extensions/trbe.h>
Manish V Badarkhe51a97112021-07-08 09:33:18 +010029#include <lib/extensions/trf.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000030#include <lib/utils.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000031
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +010032#if ENABLE_FEAT_TWED
33/* Make sure delay value fits within the range(0-15) */
34CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check);
35#endif /* ENABLE_FEAT_TWED */
Achin Gupta7aea9082014-02-01 07:51:28 +000036
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +010037static void manage_extensions_secure(cpu_context_t *ctx);
Zelalem Aweke42401112022-01-05 17:12:24 -060038/******************************************************************************
39 * This function performs initializations that are specific to SECURE state
40 * and updates the cpu context specified by 'ctx'.
41 *****************************************************************************/
42static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep)
Achin Gupta7aea9082014-02-01 07:51:28 +000043{
Zelalem Aweke42401112022-01-05 17:12:24 -060044 u_register_t scr_el3;
45 el3_state_t *state;
46
47 state = get_el3state_ctx(ctx);
48 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
49
50#if defined(IMAGE_BL31) && !defined(SPD_spmd)
Achin Gupta7aea9082014-02-01 07:51:28 +000051 /*
Zelalem Aweke42401112022-01-05 17:12:24 -060052 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
53 * indicated by the interrupt routing model for BL31.
54 */
55 scr_el3 |= get_scr_el3_from_routing_model(SECURE);
56#endif
57
58#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
59 /* Get Memory Tagging Extension support level */
60 unsigned int mte = get_armv8_5_mte_support();
61#endif
62 /*
63 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS
64 * is set, or when MTE is only implemented at EL0.
Achin Gupta7aea9082014-02-01 07:51:28 +000065 */
Zelalem Aweke42401112022-01-05 17:12:24 -060066#if CTX_INCLUDE_MTE_REGS
67 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
68 scr_el3 |= SCR_ATA_BIT;
69#else
70 if (mte == MTE_IMPLEMENTED_EL0) {
71 scr_el3 |= SCR_ATA_BIT;
72 }
73#endif /* CTX_INCLUDE_MTE_REGS */
74
75 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */
76 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) {
77 if (GET_RW(ep->spsr) != MODE_RW_64) {
78 ERROR("S-EL2 can not be used in AArch32\n.");
79 panic();
80 }
81
82 scr_el3 |= SCR_EEL2_BIT;
83 }
84
85 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
86
87 manage_extensions_secure(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +000088}
89
Zelalem Aweke42401112022-01-05 17:12:24 -060090#if ENABLE_RME
91/******************************************************************************
92 * This function performs initializations that are specific to REALM state
93 * and updates the cpu context specified by 'ctx'.
94 *****************************************************************************/
95static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
96{
97 u_register_t scr_el3;
98 el3_state_t *state;
99
100 state = get_el3state_ctx(ctx);
101 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
102
103 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT;
104
105 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
106}
107#endif /* ENABLE_RME */
108
109/******************************************************************************
110 * This function performs initializations that are specific to NON-SECURE state
111 * and updates the cpu context specified by 'ctx'.
112 *****************************************************************************/
113static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
114{
115 u_register_t scr_el3;
116 el3_state_t *state;
117
118 state = get_el3state_ctx(ctx);
119 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
120
121 /* SCR_NS: Set the NS bit */
122 scr_el3 |= SCR_NS_BIT;
123
124#if !CTX_INCLUDE_PAUTH_REGS
125 /*
126 * If the pointer authentication registers aren't saved during world
127 * switches the value of the registers can be leaked from the Secure to
128 * the Non-secure world. To prevent this, rather than enabling pointer
129 * authentication everywhere, we only enable it in the Non-secure world.
130 *
131 * If the Secure world wants to use pointer authentication,
132 * CTX_INCLUDE_PAUTH_REGS must be set to 1.
133 */
134 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
135#endif /* !CTX_INCLUDE_PAUTH_REGS */
136
137 /* Allow access to Allocation Tags when MTE is implemented. */
138 scr_el3 |= SCR_ATA_BIT;
139
140#ifdef IMAGE_BL31
141 /*
142 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
143 * indicated by the interrupt routing model for BL31.
144 */
145 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
146#endif
147 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600148
149 /* Initialize EL2 context registers */
150#if CTX_INCLUDE_EL2_REGS
151
152 /*
153 * Initialize SCTLR_EL2 context register using Endianness value
154 * taken from the entrypoint attribute.
155 */
156 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
157 sctlr_el2 |= SCTLR_EL2_RES1;
158 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2,
159 sctlr_el2);
160
161 /*
162 * The GICv3 driver initializes the ICC_SRE_EL2 register during
163 * platform setup. Use the same setting for the corresponding
164 * context register to make sure the correct bits are set when
165 * restoring NS context.
166 */
167 u_register_t icc_sre_el2 = read_icc_sre_el2();
168 icc_sre_el2 |= (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT);
169 icc_sre_el2 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
170 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2,
171 icc_sre_el2);
172#endif /* CTX_INCLUDE_EL2_REGS */
Zelalem Aweke42401112022-01-05 17:12:24 -0600173}
174
Achin Gupta7aea9082014-02-01 07:51:28 +0000175/*******************************************************************************
Zelalem Aweke42401112022-01-05 17:12:24 -0600176 * The following function performs initialization of the cpu_context 'ctx'
177 * for first use that is common to all security states, and sets the
178 * initial entrypoint state as specified by the entry_point_info structure.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100179 *
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000180 * The EE and ST attributes are used to configure the endianness and secure
Soby Mathewb0082d22015-04-09 13:40:55 +0100181 * timer availability for the new execution context.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100182 ******************************************************************************/
Zelalem Aweke42401112022-01-05 17:12:24 -0600183static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100184{
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000185 u_register_t scr_el3;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100186 el3_state_t *state;
187 gp_regs_t *gp_regs;
Deepika Bhavnanib0f26022019-09-03 21:08:51 +0300188 u_register_t sctlr_elx, actlr_elx;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100189
Andrew Thoelke4e126072014-06-04 21:10:52 +0100190 /* Clear any residual register values from the context */
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000191 zeromem(ctx, sizeof(*ctx));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100192
193 /*
David Cunadofee86532017-04-13 22:38:29 +0100194 * SCR_EL3 was initialised during reset sequence in macro
195 * el3_arch_init_common. This code modifies the SCR_EL3 fields that
196 * affect the next EL.
197 *
198 * The following fields are initially set to zero and then updated to
199 * the required value depending on the state of the SPSR_EL3 and the
200 * Security state and entrypoint attributes of the next EL.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100201 */
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000202 scr_el3 = read_scr();
Andrew Thoelke4e126072014-06-04 21:10:52 +0100203 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
Zelalem Aweke42401112022-01-05 17:12:24 -0600204 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT);
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500205
David Cunadofee86532017-04-13 22:38:29 +0100206 /*
207 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
208 * Exception level as specified by SPSR.
209 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500210 if (GET_RW(ep->spsr) == MODE_RW_64) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100211 scr_el3 |= SCR_RW_BIT;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500212 }
Zelalem Aweke42401112022-01-05 17:12:24 -0600213
David Cunadofee86532017-04-13 22:38:29 +0100214 /*
215 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
216 * Secure timer registers to EL3, from AArch64 state only, if specified
217 * by the entrypoint attributes.
218 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500219 if (EP_GET_ST(ep->h.attr) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100220 scr_el3 |= SCR_ST_BIT;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500221 }
Andrew Thoelke4e126072014-06-04 21:10:52 +0100222
johpow01f91e59f2021-08-04 19:38:18 -0500223 /*
224 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting
225 * SCR_EL3.HXEn.
226 */
227#if ENABLE_FEAT_HCX
228 scr_el3 |= SCR_HXEn_BIT;
229#endif
230
Varun Wadekar92234852020-06-12 10:11:28 -0700231#if RAS_TRAP_LOWER_EL_ERR_ACCESS
232 /*
233 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
234 * and RAS ERX registers from EL1 and EL2 are trapped to EL3.
235 */
236 scr_el3 |= SCR_TERR_BIT;
237#endif
238
Julius Wernerc51a2ec2018-08-28 14:45:43 -0700239#if !HANDLE_EA_EL3_FIRST
David Cunadofee86532017-04-13 22:38:29 +0100240 /*
241 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External
Zelalem Aweke42401112022-01-05 17:12:24 -0600242 * to EL3 when executing at a lower EL. When executing at EL3, External
243 * Aborts are taken to EL3.
David Cunadofee86532017-04-13 22:38:29 +0100244 */
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100245 scr_el3 &= ~SCR_EA_BIT;
246#endif
247
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000248#if FAULT_INJECTION_SUPPORT
249 /* Enable fault injection from lower ELs */
250 scr_el3 |= SCR_FIEN_BIT;
251#endif
252
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000253 /*
Zelalem Aweke42401112022-01-05 17:12:24 -0600254 * CPTR_EL3 was initialized out of reset, copy that value to the
255 * context register.
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000256 */
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100257 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3());
Max Shvetsovc4502772021-03-22 11:59:37 +0000258
Andrew Thoelke4e126072014-06-04 21:10:52 +0100259 /*
David Cunadofee86532017-04-13 22:38:29 +0100260 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
261 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
262 * next mode is Hyp.
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500263 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
264 * same conditions as HVC instructions and when the processor supports
265 * ARMv8.6-FGT.
Jimmy Brisson83573892020-04-16 10:48:02 -0500266 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV)
267 * CNTPOFF_EL2 register under the same conditions as HVC instructions
268 * and when the processor supports ECV.
David Cunadofee86532017-04-13 22:38:29 +0100269 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000270 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
271 || ((GET_RW(ep->spsr) != MODE_RW_64)
272 && (GET_M32(ep->spsr) == MODE32_hyp))) {
David Cunadofee86532017-04-13 22:38:29 +0100273 scr_el3 |= SCR_HCE_BIT;
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500274
275 if (is_armv8_6_fgt_present()) {
276 scr_el3 |= SCR_FGTEN_BIT;
277 }
Jimmy Brisson83573892020-04-16 10:48:02 -0500278
279 if (get_armv8_6_ecv_support()
280 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) {
281 scr_el3 |= SCR_ECVEN_BIT;
282 }
David Cunadofee86532017-04-13 22:38:29 +0100283 }
284
285 /*
johpow01fa59c6f2020-10-02 13:41:11 -0500286 * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3
287 * and EL2, when clear, this bit traps accesses from EL2 so we set it
288 * to 1 when EL2 is present.
289 */
290 if (is_armv8_6_feat_amuv1p1_present() &&
291 (el_implemented(2) != EL_IMPL_NONE)) {
292 scr_el3 |= SCR_AMVOFFEN_BIT;
293 }
294
295 /*
David Cunadofee86532017-04-13 22:38:29 +0100296 * Initialise SCTLR_EL1 to the reset value corresponding to the target
297 * execution state setting all fields rather than relying of the hw.
298 * Some fields have architecturally UNKNOWN reset values and these are
299 * set to zero.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100300 *
David Cunadofee86532017-04-13 22:38:29 +0100301 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100302 *
David Cunadofee86532017-04-13 22:38:29 +0100303 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
304 * required by PSCI specification)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100305 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000306 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500307 if (GET_RW(ep->spsr) == MODE_RW_64) {
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200308 sctlr_elx |= SCTLR_EL1_RES1;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500309 } else {
Soby Mathewa993c422016-09-29 14:15:57 +0100310 /*
David Cunadofee86532017-04-13 22:38:29 +0100311 * If the target execution state is AArch32 then the following
312 * fields need to be set.
313 *
314 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
315 * instructions are not trapped to EL1.
316 *
317 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
318 * instructions are not trapped to EL1.
319 *
320 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
321 * CP15DMB, CP15DSB, and CP15ISB instructions.
Soby Mathewa993c422016-09-29 14:15:57 +0100322 */
David Cunadofee86532017-04-13 22:38:29 +0100323 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
324 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
Soby Mathewa993c422016-09-29 14:15:57 +0100325 }
326
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000327#if ERRATA_A75_764081
328 /*
329 * If workaround of errata 764081 for Cortex-A75 is used then set
330 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
331 */
332 sctlr_elx |= SCTLR_IESB_BIT;
333#endif
334
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100335#if ENABLE_FEAT_TWED
johpow013e24c162020-04-22 14:05:13 -0500336 /* Enable WFE trap delay in SCR_EL3 if supported and configured */
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100337 /* Set delay in SCR_EL3 */
338 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
339 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK)
340 << SCR_TWEDEL_SHIFT);
johpow013e24c162020-04-22 14:05:13 -0500341
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100342 /* Enable WFE delay */
343 scr_el3 |= SCR_TWEDEn_BIT;
344#endif /* ENABLE_FEAT_TWED */
johpow013e24c162020-04-22 14:05:13 -0500345
David Cunadofee86532017-04-13 22:38:29 +0100346 /*
347 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
Olivier Deprez7d0299f2021-05-25 12:06:03 +0200348 * and other EL2 registers are set up by cm_prepare_el3_exit() as they
David Cunadofee86532017-04-13 22:38:29 +0100349 * are not part of the stored cpu_context.
350 */
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000351 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100352
Varun Wadekarb6dd0b32018-05-08 10:52:36 -0700353 /*
354 * Base the context ACTLR_EL1 on the current value, as it is
355 * implementation defined. The context restore process will write
356 * the value from the context to the actual register and can cause
357 * problems for processor cores that don't expect certain bits to
358 * be zero.
359 */
360 actlr_elx = read_actlr_el1();
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000361 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
Varun Wadekarb6dd0b32018-05-08 10:52:36 -0700362
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100363 /*
364 * Populate EL3 state so that we've the right context
365 * before doing ERET
366 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100367 state = get_el3state_ctx(ctx);
368 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
369 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
370 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
371
372 /*
373 * Store the X0-X7 value from the entrypoint into the context
374 * Use memcpy as we are in control of the layout of the structures
375 */
376 gp_regs = get_gpregs_ctx(ctx);
377 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
378}
379
380/*******************************************************************************
Zelalem Aweke42401112022-01-05 17:12:24 -0600381 * Context management library initialization routine. This library is used by
382 * runtime services to share pointers to 'cpu_context' structures for secure
383 * non-secure and realm states. Management of the structures and their associated
384 * memory is not done by the context management library e.g. the PSCI service
385 * manages the cpu context used for entry from and exit to the non-secure state.
386 * The Secure payload dispatcher service manages the context(s) corresponding to
387 * the secure state. It also uses this library to get access to the non-secure
388 * state cpu context pointers.
389 * Lastly, this library provides the API to make SP_EL3 point to the cpu context
390 * which will be used for programming an entry into a lower EL. The same context
391 * will be used to save state upon exception entry from that EL.
392 ******************************************************************************/
393void __init cm_init(void)
394{
395 /*
396 * The context management library has only global data to intialize, but
397 * that will be done when the BSS is zeroed out.
398 */
399}
400
401/*******************************************************************************
402 * This is the high-level function used to initialize the cpu_context 'ctx' for
403 * first use. It performs initializations that are common to all security states
404 * and initializations specific to the security state specified in 'ep'
405 ******************************************************************************/
406void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
407{
408 unsigned int security_state;
409
410 assert(ctx != NULL);
411
412 /*
413 * Perform initializations that are common
414 * to all security states
415 */
416 setup_context_common(ctx, ep);
417
418 security_state = GET_SECURITY_STATE(ep->h.attr);
419
420 /* Perform security state specific initializations */
421 switch (security_state) {
422 case SECURE:
423 setup_secure_context(ctx, ep);
424 break;
425#if ENABLE_RME
426 case REALM:
427 setup_realm_context(ctx, ep);
428 break;
429#endif
430 case NON_SECURE:
431 setup_ns_context(ctx, ep);
432 break;
433 default:
434 ERROR("Invalid security state\n");
435 panic();
436 break;
437 }
438}
439
440/*******************************************************************************
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000441 * Enable architecture extensions on first entry to Non-secure world.
442 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
443 * it is zero.
444 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -0500445static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000446{
447#if IMAGE_BL31
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100448#if ENABLE_SPE_FOR_LOWER_ELS
449 spe_enable(el2_unused);
450#endif
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100451
452#if ENABLE_AMU
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100453 amu_enable(el2_unused, ctx);
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100454#endif
David Cunadoce88eee2017-10-20 11:30:57 +0100455
johpow019baade32021-07-08 14:14:00 -0500456#if ENABLE_SME_FOR_NS
457 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */
458 sme_enable(ctx);
459#elif ENABLE_SVE_FOR_NS
460 /* Enable SVE and FPU/SIMD for non-secure world. */
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100461 sve_enable(ctx);
462#endif
463
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100464#if ENABLE_MPAM_FOR_LOWER_ELS
465 mpam_enable(el2_unused);
466#endif
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100467
468#if ENABLE_TRBE_FOR_NS
469 trbe_enable();
470#endif /* ENABLE_TRBE_FOR_NS */
471
Manish V Badarkhef356f7e2021-06-29 11:44:20 +0100472#if ENABLE_SYS_REG_TRACE_FOR_NS
473 sys_reg_trace_enable(ctx);
474#endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
475
Manish V Badarkhe51a97112021-07-08 09:33:18 +0100476#if ENABLE_TRF_FOR_NS
477 trf_enable();
478#endif /* ENABLE_TRF_FOR_NS */
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000479#endif
480}
481
482/*******************************************************************************
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100483 * Enable architecture extensions on first entry to Secure world.
484 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -0500485static void manage_extensions_secure(cpu_context_t *ctx)
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100486{
487#if IMAGE_BL31
johpow019baade32021-07-08 14:14:00 -0500488 #if ENABLE_SME_FOR_NS
489 #if ENABLE_SME_FOR_SWD
490 /*
491 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must
492 * ensure SME, SVE, and FPU/SIMD context properly managed.
493 */
494 sme_enable(ctx);
495 #else /* ENABLE_SME_FOR_SWD */
496 /*
497 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can
498 * safely use the associated registers.
499 */
500 sme_disable(ctx);
501 #endif /* ENABLE_SME_FOR_SWD */
502 #elif ENABLE_SVE_FOR_NS
503 #if ENABLE_SVE_FOR_SWD
504 /*
505 * Enable SVE and FPU in secure context, secure manager must ensure that
506 * the SVE and FPU register contexts are properly managed.
507 */
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100508 sve_enable(ctx);
johpow019baade32021-07-08 14:14:00 -0500509 #else /* ENABLE_SVE_FOR_SWD */
510 /*
511 * Disable SVE and FPU in secure context so non-secure world can safely
512 * use them.
513 */
514 sve_disable(ctx);
515 #endif /* ENABLE_SVE_FOR_SWD */
516 #endif /* ENABLE_SVE_FOR_NS */
517#endif /* IMAGE_BL31 */
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100518}
519
520/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +0100521 * The following function initializes the cpu_context for a CPU specified by
522 * its `cpu_idx` for first use, and sets the initial entrypoint state as
523 * specified by the entry_point_info structure.
524 ******************************************************************************/
525void cm_init_context_by_index(unsigned int cpu_idx,
526 const entry_point_info_t *ep)
527{
528 cpu_context_t *ctx;
529 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100530 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100531}
532
533/*******************************************************************************
534 * The following function initializes the cpu_context for the current CPU
535 * for first use, and sets the initial entrypoint state as specified by the
536 * entry_point_info structure.
537 ******************************************************************************/
538void cm_init_my_context(const entry_point_info_t *ep)
539{
540 cpu_context_t *ctx;
541 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100542 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100543}
544
545/*******************************************************************************
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500546 * Prepare the CPU system registers for first entry into realm, secure, or
547 * normal world.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100548 *
549 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
550 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
551 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
552 * For all entries, the EL1 registers are initialized from the cpu_context
553 ******************************************************************************/
554void cm_prepare_el3_exit(uint32_t security_state)
555{
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000556 u_register_t sctlr_elx, scr_el3, mdcr_el2;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100557 cpu_context_t *ctx = cm_get_context(security_state);
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100558 bool el2_unused = false;
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000559 uint64_t hcr_el2 = 0U;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100560
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000561 assert(ctx != NULL);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100562
563 if (security_state == NON_SECURE) {
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000564 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000565 CTX_SCR_EL3);
566 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100567 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000568 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000569 CTX_SCTLR_EL1);
Ken Kuang00eac152017-08-23 16:03:29 +0800570 sctlr_elx &= SCTLR_EE_BIT;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100571 sctlr_elx |= SCTLR_EL2_RES1;
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000572#if ERRATA_A75_764081
573 /*
574 * If workaround of errata 764081 for Cortex-A75 is used
575 * then set SCTLR_EL2.IESB to enable Implicit Error
576 * Synchronization Barrier.
577 */
578 sctlr_elx |= SCTLR_IESB_BIT;
579#endif
Andrew Thoelke4e126072014-06-04 21:10:52 +0100580 write_sctlr_el2(sctlr_elx);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000581 } else if (el_implemented(2) != EL_IMPL_NONE) {
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100582 el2_unused = true;
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000583
David Cunadofee86532017-04-13 22:38:29 +0100584 /*
585 * EL2 present but unused, need to disable safely.
586 * SCTLR_EL2 can be ignored in this case.
587 *
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100588 * Set EL2 register width appropriately: Set HCR_EL2
589 * field to match SCR_EL3.RW.
David Cunadofee86532017-04-13 22:38:29 +0100590 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000591 if ((scr_el3 & SCR_RW_BIT) != 0U)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100592 hcr_el2 |= HCR_RW_BIT;
593
594 /*
595 * For Armv8.3 pointer authentication feature, disable
596 * traps to EL2 when accessing key registers or using
597 * pointer authentication instructions from lower ELs.
598 */
599 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
600
601 write_hcr_el2(hcr_el2);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100602
David Cunadofee86532017-04-13 22:38:29 +0100603 /*
604 * Initialise CPTR_EL2 setting all fields rather than
605 * relying on the hw. All fields have architecturally
606 * UNKNOWN reset values.
607 *
608 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
609 * accesses to the CPACR_EL1 or CPACR from both
610 * Execution states do not trap to EL2.
611 *
612 * CPTR_EL2.TTA: Set to zero so that Non-secure System
613 * register accesses to the trace registers from both
614 * Execution states do not trap to EL2.
Manish V Badarkhef356f7e2021-06-29 11:44:20 +0100615 * If PE trace unit System registers are not implemented
616 * then this bit is reserved, and must be set to zero.
David Cunadofee86532017-04-13 22:38:29 +0100617 *
618 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
619 * to SIMD and floating-point functionality from both
620 * Execution states do not trap to EL2.
621 */
622 write_cptr_el2(CPTR_EL2_RESET_VAL &
623 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
624 | CPTR_EL2_TFP_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100625
David Cunadofee86532017-04-13 22:38:29 +0100626 /*
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000627 * Initialise CNTHCTL_EL2. All fields are
David Cunadofee86532017-04-13 22:38:29 +0100628 * architecturally UNKNOWN on reset and are set to zero
629 * except for field(s) listed below.
630 *
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500631 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to
David Cunadofee86532017-04-13 22:38:29 +0100632 * Hyp mode of Non-secure EL0 and EL1 accesses to the
633 * physical timer registers.
634 *
635 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
636 * Hyp mode of Non-secure EL0 and EL1 accesses to the
637 * physical counter registers.
638 */
639 write_cnthctl_el2(CNTHCTL_RESET_VAL |
640 EL1PCEN_BIT | EL1PCTEN_BIT);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100641
David Cunadofee86532017-04-13 22:38:29 +0100642 /*
643 * Initialise CNTVOFF_EL2 to zero as it resets to an
644 * architecturally UNKNOWN value.
645 */
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100646 write_cntvoff_el2(0);
647
David Cunadofee86532017-04-13 22:38:29 +0100648 /*
649 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
650 * MPIDR_EL1 respectively.
651 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100652 write_vpidr_el2(read_midr_el1());
653 write_vmpidr_el2(read_mpidr_el1());
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000654
655 /*
David Cunadofee86532017-04-13 22:38:29 +0100656 * Initialise VTTBR_EL2. All fields are architecturally
657 * UNKNOWN on reset.
658 *
659 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
660 * 2 address translation is disabled, cache maintenance
661 * operations depend on the VMID.
662 *
663 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
664 * translation is disabled.
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000665 */
David Cunadofee86532017-04-13 22:38:29 +0100666 write_vttbr_el2(VTTBR_RESET_VAL &
667 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
668 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
669
David Cunado5f55e282016-10-31 17:37:34 +0000670 /*
David Cunadofee86532017-04-13 22:38:29 +0100671 * Initialise MDCR_EL2, setting all fields rather than
672 * relying on hw. Some fields are architecturally
673 * UNKNOWN on reset.
674 *
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100675 * MDCR_EL2.HLP: Set to one so that event counter
676 * overflow, that is recorded in PMOVSCLR_EL0[0-30],
677 * occurs on the increment that changes
678 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is
679 * implemented. This bit is RES0 in versions of the
680 * architecture earlier than ARMv8.5, setting it to 1
681 * doesn't have any effect on them.
682 *
683 * MDCR_EL2.TTRF: Set to zero so that access to Trace
684 * Filter Control register TRFCR_EL1 at EL1 is not
685 * trapped to EL2. This bit is RES0 in versions of
686 * the architecture earlier than ARMv8.4.
687 *
688 * MDCR_EL2.HPMD: Set to one so that event counting is
689 * prohibited at EL2. This bit is RES0 in versions of
690 * the architecture earlier than ARMv8.1, setting it
691 * to 1 doesn't have any effect on them.
692 *
693 * MDCR_EL2.TPMS: Set to zero so that accesses to
694 * Statistical Profiling control registers from EL1
695 * do not trap to EL2. This bit is RES0 when SPE is
696 * not implemented.
697 *
David Cunadofee86532017-04-13 22:38:29 +0100698 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
699 * EL1 System register accesses to the Debug ROM
700 * registers are not trapped to EL2.
701 *
702 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
703 * System register accesses to the powerdown debug
704 * registers are not trapped to EL2.
705 *
706 * MDCR_EL2.TDA: Set to zero so that System register
707 * accesses to the debug registers do not trap to EL2.
708 *
709 * MDCR_EL2.TDE: Set to zero so that debug exceptions
710 * are not routed to EL2.
711 *
712 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance
713 * Monitors.
714 *
715 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
716 * EL1 accesses to all Performance Monitors registers
717 * are not trapped to EL2.
718 *
719 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
720 * and EL1 accesses to the PMCR_EL0 or PMCR are not
721 * trapped to EL2.
722 *
723 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
724 * architecturally-defined reset value.
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100725 *
726 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer
727 * owning exception level is NS-EL1 and, tracing is
728 * prohibited at NS-EL2. These bits are RES0 when
729 * FEAT_TRBE is not implemented.
David Cunado5f55e282016-10-31 17:37:34 +0000730 */
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100731 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP |
732 MDCR_EL2_HPMD) |
733 ((read_pmcr_el0() & PMCR_EL0_N_BITS)
734 >> PMCR_EL0_N_SHIFT)) &
735 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS |
736 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
737 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
738 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT |
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100739 MDCR_EL2_TPMCR_BIT |
740 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
dp-armee3457b2017-05-23 09:32:49 +0100741
dp-armee3457b2017-05-23 09:32:49 +0100742 write_mdcr_el2(mdcr_el2);
743
David Cunadoc14b08e2016-11-25 00:21:59 +0000744 /*
David Cunadofee86532017-04-13 22:38:29 +0100745 * Initialise HSTR_EL2. All fields are architecturally
746 * UNKNOWN on reset.
747 *
748 * HSTR_EL2.T<n>: Set all these fields to zero so that
749 * Non-secure EL0 or EL1 accesses to System registers
750 * do not trap to EL2.
David Cunadoc14b08e2016-11-25 00:21:59 +0000751 */
David Cunadofee86532017-04-13 22:38:29 +0100752 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
David Cunadoc14b08e2016-11-25 00:21:59 +0000753 /*
David Cunadofee86532017-04-13 22:38:29 +0100754 * Initialise CNTHP_CTL_EL2. All fields are
755 * architecturally UNKNOWN on reset.
756 *
757 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
758 * physical timer and prevent timer interrupts.
David Cunadoc14b08e2016-11-25 00:21:59 +0000759 */
David Cunadofee86532017-04-13 22:38:29 +0100760 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
761 ~(CNTHP_CTL_ENABLE_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100762 }
johpow019baade32021-07-08 14:14:00 -0500763 manage_extensions_nonsecure(el2_unused, ctx);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100764 }
765
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100766 cm_el1_sysregs_context_restore(security_state);
767 cm_set_next_eret_context(security_state);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100768}
769
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000770#if CTX_INCLUDE_EL2_REGS
771/*******************************************************************************
772 * Save EL2 sysreg context
773 ******************************************************************************/
774void cm_el2_sysregs_context_save(uint32_t security_state)
775{
776 u_register_t scr_el3 = read_scr();
777
778 /*
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500779 * Always save the non-secure and realm EL2 context, only save the
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000780 * S-EL2 context if S-EL2 is enabled.
781 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500782 if ((security_state != SECURE) ||
Ruari Phipps4283ed12020-07-28 11:26:29 +0100783 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) {
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000784 cpu_context_t *ctx;
785
786 ctx = cm_get_context(security_state);
787 assert(ctx != NULL);
788
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000789 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx));
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000790 }
791}
792
793/*******************************************************************************
794 * Restore EL2 sysreg context
795 ******************************************************************************/
796void cm_el2_sysregs_context_restore(uint32_t security_state)
797{
798 u_register_t scr_el3 = read_scr();
799
800 /*
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500801 * Always restore the non-secure and realm EL2 context, only restore the
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000802 * S-EL2 context if S-EL2 is enabled.
803 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500804 if ((security_state != SECURE) ||
Ruari Phipps4283ed12020-07-28 11:26:29 +0100805 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) {
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000806 cpu_context_t *ctx;
807
808 ctx = cm_get_context(security_state);
809 assert(ctx != NULL);
810
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000811 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx));
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000812 }
813}
814#endif /* CTX_INCLUDE_EL2_REGS */
815
Andrew Thoelke4e126072014-06-04 21:10:52 +0100816/*******************************************************************************
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600817 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
818 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
819 * updating EL1 and EL2 registers. Otherwise, it calls the generic
820 * cm_prepare_el3_exit function.
821 ******************************************************************************/
822void cm_prepare_el3_exit_ns(void)
823{
824#if CTX_INCLUDE_EL2_REGS
825 cpu_context_t *ctx = cm_get_context(NON_SECURE);
826 assert(ctx != NULL);
827
828 /*
829 * Currently some extensions are configured using
830 * direct register updates. Therefore, do this here
831 * instead of when setting up context.
832 */
833 manage_extensions_nonsecure(0, ctx);
834
835 /*
836 * Set the NS bit to be able to access the ICC_SRE_EL2
837 * register when restoring context.
838 */
839 write_scr_el3(read_scr_el3() | SCR_NS_BIT);
840
841 /* Restore EL2 and EL1 sysreg contexts */
842 cm_el2_sysregs_context_restore(NON_SECURE);
843 cm_el1_sysregs_context_restore(NON_SECURE);
844 cm_set_next_eret_context(NON_SECURE);
845#else
846 cm_prepare_el3_exit(NON_SECURE);
847#endif /* CTX_INCLUDE_EL2_REGS */
848}
849
850/*******************************************************************************
Soby Mathew2ed46e92014-07-04 16:02:26 +0100851 * The next four functions are used by runtime services to save and restore
852 * EL1 context on the 'cpu_context' structure for the specified security
Achin Gupta7aea9082014-02-01 07:51:28 +0000853 * state.
854 ******************************************************************************/
Achin Gupta7aea9082014-02-01 07:51:28 +0000855void cm_el1_sysregs_context_save(uint32_t security_state)
856{
Dan Handleye2712bc2014-04-10 15:37:22 +0100857 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000858
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100859 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000860 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000861
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000862 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100863
864#if IMAGE_BL31
865 if (security_state == SECURE)
866 PUBLISH_EVENT(cm_exited_secure_world);
867 else
868 PUBLISH_EVENT(cm_exited_normal_world);
869#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000870}
871
872void cm_el1_sysregs_context_restore(uint32_t security_state)
873{
Dan Handleye2712bc2014-04-10 15:37:22 +0100874 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000875
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100876 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000877 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000878
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000879 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100880
881#if IMAGE_BL31
882 if (security_state == SECURE)
883 PUBLISH_EVENT(cm_entering_secure_world);
884 else
885 PUBLISH_EVENT(cm_entering_normal_world);
886#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000887}
888
889/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100890 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
891 * given security state with the given entrypoint
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000892 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +0100893void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000894{
Dan Handleye2712bc2014-04-10 15:37:22 +0100895 cpu_context_t *ctx;
896 el3_state_t *state;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000897
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100898 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000899 assert(ctx != NULL);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000900
Andrew Thoelke4e126072014-06-04 21:10:52 +0100901 /* Populate EL3 state so that ERET jumps to the correct entry */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000902 state = get_el3state_ctx(ctx);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000903 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000904}
905
906/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100907 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
908 * pertaining to the given security state
Achin Gupta607084e2014-02-09 18:24:19 +0000909 ******************************************************************************/
Andrew Thoelke4e126072014-06-04 21:10:52 +0100910void cm_set_elr_spsr_el3(uint32_t security_state,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100911 uintptr_t entrypoint, uint32_t spsr)
Achin Gupta607084e2014-02-09 18:24:19 +0000912{
Dan Handleye2712bc2014-04-10 15:37:22 +0100913 cpu_context_t *ctx;
914 el3_state_t *state;
Achin Gupta607084e2014-02-09 18:24:19 +0000915
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100916 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000917 assert(ctx != NULL);
Achin Gupta607084e2014-02-09 18:24:19 +0000918
919 /* Populate EL3 state so that ERET jumps to the correct entry */
920 state = get_el3state_ctx(ctx);
921 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100922 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
Achin Gupta607084e2014-02-09 18:24:19 +0000923}
924
925/*******************************************************************************
Achin Gupta27b895e2014-05-04 18:38:28 +0100926 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
927 * pertaining to the given security state using the value and bit position
928 * specified in the parameters. It preserves all other bits.
929 ******************************************************************************/
930void cm_write_scr_el3_bit(uint32_t security_state,
931 uint32_t bit_pos,
932 uint32_t value)
933{
934 cpu_context_t *ctx;
935 el3_state_t *state;
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000936 u_register_t scr_el3;
Achin Gupta27b895e2014-05-04 18:38:28 +0100937
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100938 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000939 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +0100940
941 /* Ensure that the bit position is a valid one */
Jimmy Brissoned202072020-08-04 16:18:52 -0500942 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
Achin Gupta27b895e2014-05-04 18:38:28 +0100943
944 /* Ensure that the 'value' is only a bit wide */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000945 assert(value <= 1U);
Achin Gupta27b895e2014-05-04 18:38:28 +0100946
947 /*
948 * Get the SCR_EL3 value from the cpu context, clear the desired bit
949 * and set it to its new value.
950 */
951 state = get_el3state_ctx(ctx);
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000952 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
Jimmy Brissoned202072020-08-04 16:18:52 -0500953 scr_el3 &= ~(1UL << bit_pos);
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000954 scr_el3 |= (u_register_t)value << bit_pos;
Achin Gupta27b895e2014-05-04 18:38:28 +0100955 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
956}
957
958/*******************************************************************************
959 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
960 * given security state.
961 ******************************************************************************/
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000962u_register_t cm_get_scr_el3(uint32_t security_state)
Achin Gupta27b895e2014-05-04 18:38:28 +0100963{
964 cpu_context_t *ctx;
965 el3_state_t *state;
966
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100967 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000968 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +0100969
970 /* Populate EL3 state so that ERET jumps to the correct entry */
971 state = get_el3state_ctx(ctx);
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000972 return read_ctx_reg(state, CTX_SCR_EL3);
Achin Gupta27b895e2014-05-04 18:38:28 +0100973}
974
975/*******************************************************************************
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000976 * This function is used to program the context that's used for exception
977 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
978 * the required security state
Achin Gupta7aea9082014-02-01 07:51:28 +0000979 ******************************************************************************/
980void cm_set_next_eret_context(uint32_t security_state)
981{
Dan Handleye2712bc2014-04-10 15:37:22 +0100982 cpu_context_t *ctx;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000983
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100984 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000985 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000986
Andrew Thoelke4e126072014-06-04 21:10:52 +0100987 cm_set_next_context(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +0000988}