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Achin Gupta9ac63c52014-01-16 12:08:03 +00001/*
Dimitris Papastamosb63c6f12018-01-11 15:29:36 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta9ac63c52014-01-16 12:08:03 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta9ac63c52014-01-16 12:08:03 +00005 */
6
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00007#ifndef CONTEXT_H
8#define CONTEXT_H
Achin Gupta9ac63c52014-01-16 12:08:03 +00009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000011
Achin Gupta9ac63c52014-01-16 12:08:03 +000012/*******************************************************************************
Achin Gupta07f4e072014-02-02 12:02:23 +000013 * Constants that allow assembler code to access members of and the 'gp_regs'
14 * structure at their correct offsets.
15 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070016#define CTX_GPREGS_OFFSET U(0x0)
17#define CTX_GPREG_X0 U(0x0)
18#define CTX_GPREG_X1 U(0x8)
19#define CTX_GPREG_X2 U(0x10)
20#define CTX_GPREG_X3 U(0x18)
21#define CTX_GPREG_X4 U(0x20)
22#define CTX_GPREG_X5 U(0x28)
23#define CTX_GPREG_X6 U(0x30)
24#define CTX_GPREG_X7 U(0x38)
25#define CTX_GPREG_X8 U(0x40)
26#define CTX_GPREG_X9 U(0x48)
27#define CTX_GPREG_X10 U(0x50)
28#define CTX_GPREG_X11 U(0x58)
29#define CTX_GPREG_X12 U(0x60)
30#define CTX_GPREG_X13 U(0x68)
31#define CTX_GPREG_X14 U(0x70)
32#define CTX_GPREG_X15 U(0x78)
33#define CTX_GPREG_X16 U(0x80)
34#define CTX_GPREG_X17 U(0x88)
35#define CTX_GPREG_X18 U(0x90)
36#define CTX_GPREG_X19 U(0x98)
37#define CTX_GPREG_X20 U(0xa0)
38#define CTX_GPREG_X21 U(0xa8)
39#define CTX_GPREG_X22 U(0xb0)
40#define CTX_GPREG_X23 U(0xb8)
41#define CTX_GPREG_X24 U(0xc0)
42#define CTX_GPREG_X25 U(0xc8)
43#define CTX_GPREG_X26 U(0xd0)
44#define CTX_GPREG_X27 U(0xd8)
45#define CTX_GPREG_X28 U(0xe0)
46#define CTX_GPREG_X29 U(0xe8)
47#define CTX_GPREG_LR U(0xf0)
48#define CTX_GPREG_SP_EL0 U(0xf8)
49#define CTX_GPREGS_END U(0x100)
Achin Gupta07f4e072014-02-02 12:02:23 +000050
51/*******************************************************************************
Achin Gupta9ac63c52014-01-16 12:08:03 +000052 * Constants that allow assembler code to access members of and the 'el3_state'
53 * structure at their correct offsets. Note that some of the registers are only
54 * 32-bits wide but are stored as 64-bit values for convenience
55 ******************************************************************************/
Dimitris Papastamosb63c6f12018-01-11 15:29:36 +000056#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070057#define CTX_SCR_EL3 U(0x0)
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000058#define CTX_ESR_EL3 U(0x8)
59#define CTX_RUNTIME_SP U(0x10)
60#define CTX_SPSR_EL3 U(0x18)
61#define CTX_ELR_EL3 U(0x20)
62#define CTX_UNUSED U(0x28)
63#define CTX_EL3STATE_END U(0x30)
Achin Gupta9ac63c52014-01-16 12:08:03 +000064
65/*******************************************************************************
66 * Constants that allow assembler code to access members of and the
67 * 'el1_sys_regs' structure at their correct offsets. Note that some of the
68 * registers are only 32-bits wide but are stored as 64-bit values for
69 * convenience
70 ******************************************************************************/
71#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070072#define CTX_SPSR_EL1 U(0x0)
73#define CTX_ELR_EL1 U(0x8)
74#define CTX_SCTLR_EL1 U(0x10)
75#define CTX_ACTLR_EL1 U(0x18)
76#define CTX_CPACR_EL1 U(0x20)
77#define CTX_CSSELR_EL1 U(0x28)
78#define CTX_SP_EL1 U(0x30)
79#define CTX_ESR_EL1 U(0x38)
80#define CTX_TTBR0_EL1 U(0x40)
81#define CTX_TTBR1_EL1 U(0x48)
82#define CTX_MAIR_EL1 U(0x50)
83#define CTX_AMAIR_EL1 U(0x58)
84#define CTX_TCR_EL1 U(0x60)
85#define CTX_TPIDR_EL1 U(0x68)
86#define CTX_TPIDR_EL0 U(0x70)
87#define CTX_TPIDRRO_EL0 U(0x78)
88#define CTX_PAR_EL1 U(0x80)
89#define CTX_FAR_EL1 U(0x88)
90#define CTX_AFSR0_EL1 U(0x90)
91#define CTX_AFSR1_EL1 U(0x98)
92#define CTX_CONTEXTIDR_EL1 U(0xa0)
93#define CTX_VBAR_EL1 U(0xa8)
David Cunado4168f2f2017-10-02 17:41:39 +010094#define CTX_PMCR_EL0 U(0xb0)
Soby Mathewd75d2ba2016-05-17 14:01:32 +010095
96/*
97 * If the platform is AArch64-only, there is no need to save and restore these
98 * AArch32 registers.
99 */
100#if CTX_INCLUDE_AARCH32_REGS
David Cunado4168f2f2017-10-02 17:41:39 +0100101#define CTX_SPSR_ABT U(0xc0) /* Align to the next 16 byte boundary */
102#define CTX_SPSR_UND U(0xc8)
103#define CTX_SPSR_IRQ U(0xd0)
104#define CTX_SPSR_FIQ U(0xd8)
105#define CTX_DACR32_EL2 U(0xe0)
106#define CTX_IFSR32_EL2 U(0xe8)
David Cunadod1a1fd42017-10-20 11:30:57 +0100107#define CTX_TIMER_SYSREGS_OFF U(0xf0) /* Align to the next 16 byte boundary */
Soby Mathewd75d2ba2016-05-17 14:01:32 +0100108#else
David Cunado4168f2f2017-10-02 17:41:39 +0100109#define CTX_TIMER_SYSREGS_OFF U(0xc0) /* Align to the next 16 byte boundary */
Soby Mathewd75d2ba2016-05-17 14:01:32 +0100110#endif /* __CTX_INCLUDE_AARCH32_REGS__ */
111
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100112/*
113 * If the timer registers aren't saved and restored, we don't have to reserve
114 * space for them in the context
115 */
116#if NS_TIMER_SWITCH
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700117#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x0))
118#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x8))
119#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x10))
120#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x18))
121#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + U(0x20))
122#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + U(0x30)) /* Align to the next 16 byte boundary */
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100123#else
Soby Mathewd75d2ba2016-05-17 14:01:32 +0100124#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF
125#endif /* __NS_TIMER_SWITCH__ */
Achin Gupta9ac63c52014-01-16 12:08:03 +0000126
127/*******************************************************************************
128 * Constants that allow assembler code to access members of and the 'fp_regs'
129 * structure at their correct offsets.
130 ******************************************************************************/
131#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END)
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100132#if CTX_INCLUDE_FPREGS
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700133#define CTX_FP_Q0 U(0x0)
134#define CTX_FP_Q1 U(0x10)
135#define CTX_FP_Q2 U(0x20)
136#define CTX_FP_Q3 U(0x30)
137#define CTX_FP_Q4 U(0x40)
138#define CTX_FP_Q5 U(0x50)
139#define CTX_FP_Q6 U(0x60)
140#define CTX_FP_Q7 U(0x70)
141#define CTX_FP_Q8 U(0x80)
142#define CTX_FP_Q9 U(0x90)
143#define CTX_FP_Q10 U(0xa0)
144#define CTX_FP_Q11 U(0xb0)
145#define CTX_FP_Q12 U(0xc0)
146#define CTX_FP_Q13 U(0xd0)
147#define CTX_FP_Q14 U(0xe0)
148#define CTX_FP_Q15 U(0xf0)
149#define CTX_FP_Q16 U(0x100)
150#define CTX_FP_Q17 U(0x110)
151#define CTX_FP_Q18 U(0x120)
152#define CTX_FP_Q19 U(0x130)
153#define CTX_FP_Q20 U(0x140)
154#define CTX_FP_Q21 U(0x150)
155#define CTX_FP_Q22 U(0x160)
156#define CTX_FP_Q23 U(0x170)
157#define CTX_FP_Q24 U(0x180)
158#define CTX_FP_Q25 U(0x190)
159#define CTX_FP_Q26 U(0x1a0)
160#define CTX_FP_Q27 U(0x1b0)
161#define CTX_FP_Q28 U(0x1c0)
162#define CTX_FP_Q29 U(0x1d0)
163#define CTX_FP_Q30 U(0x1e0)
164#define CTX_FP_Q31 U(0x1f0)
165#define CTX_FP_FPSR U(0x200)
166#define CTX_FP_FPCR U(0x208)
David Cunadod1a1fd42017-10-20 11:30:57 +0100167#if CTX_INCLUDE_AARCH32_REGS
168#define CTX_FP_FPEXC32_EL2 U(0x210)
169#define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */
170#else
171#define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */
172#endif
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100173#else
174#define CTX_FPREGS_END U(0)
Juan Castillo258e94f2014-06-25 17:26:36 +0100175#endif
Achin Gupta9ac63c52014-01-16 12:08:03 +0000176
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100177#define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END)
178#define CTX_CVE_2018_3639_DISABLE U(0)
179#define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */
180
Achin Gupta9ac63c52014-01-16 12:08:03 +0000181#ifndef __ASSEMBLY__
182
Dan Handley2bd4ef22014-04-09 13:14:54 +0100183#include <stdint.h>
184
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000185#include <platform_def.h> /* for CACHE_WRITEBACK_GRANULE */
186
187#include <lib/cassert.h>
188
Achin Gupta9ac63c52014-01-16 12:08:03 +0000189/*
190 * Common constants to help define the 'cpu_context' structure and its
191 * members below.
192 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700193#define DWORD_SHIFT U(3)
Achin Gupta9ac63c52014-01-16 12:08:03 +0000194#define DEFINE_REG_STRUCT(name, num_regs) \
Dan Handleye2712bc2014-04-10 15:37:22 +0100195 typedef struct name { \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000196 uint64_t _regs[num_regs]; \
Dan Handleye2712bc2014-04-10 15:37:22 +0100197 } __aligned(16) name##_t
Achin Gupta9ac63c52014-01-16 12:08:03 +0000198
199/* Constants to determine the size of individual context structures */
Achin Gupta07f4e072014-02-02 12:02:23 +0000200#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT)
Achin Gupta9ac63c52014-01-16 12:08:03 +0000201#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT)
Juan Castillo258e94f2014-06-25 17:26:36 +0100202#if CTX_INCLUDE_FPREGS
Achin Gupta9ac63c52014-01-16 12:08:03 +0000203#define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT)
Juan Castillo258e94f2014-06-25 17:26:36 +0100204#endif
Achin Gupta9ac63c52014-01-16 12:08:03 +0000205#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT)
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100206#define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT)
Achin Gupta9ac63c52014-01-16 12:08:03 +0000207
208/*
Soby Mathew6c5192a2014-04-30 15:36:37 +0100209 * AArch64 general purpose register context structure. Usually x0-x18,
210 * lr are saved as the compiler is expected to preserve the remaining
Achin Gupta07f4e072014-02-02 12:02:23 +0000211 * callee saved registers if used by the C runtime and the assembler
Soby Mathew6c5192a2014-04-30 15:36:37 +0100212 * does not touch the remaining. But in case of world switch during
213 * exception handling, we need to save the callee registers too.
Achin Gupta07f4e072014-02-02 12:02:23 +0000214 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000215DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL);
Achin Gupta07f4e072014-02-02 12:02:23 +0000216
217/*
Achin Gupta9ac63c52014-01-16 12:08:03 +0000218 * AArch64 EL1 system register context structure for preserving the
219 * architectural state during switches from one security state to
220 * another in EL1.
221 */
222DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL);
223
224/*
225 * AArch64 floating point register context structure for preserving
226 * the floating point state during switches from one security state to
227 * another.
228 */
Juan Castillo258e94f2014-06-25 17:26:36 +0100229#if CTX_INCLUDE_FPREGS
Achin Gupta9ac63c52014-01-16 12:08:03 +0000230DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL);
Juan Castillo258e94f2014-06-25 17:26:36 +0100231#endif
Achin Gupta9ac63c52014-01-16 12:08:03 +0000232
233/*
234 * Miscellaneous registers used by EL3 firmware to maintain its state
235 * across exception entries and exits
236 */
237DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL);
238
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100239/* Function pointer used by CVE-2018-3639 dynamic mitigation */
240DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL);
241
Achin Gupta9ac63c52014-01-16 12:08:03 +0000242/*
243 * Macros to access members of any of the above structures using their
244 * offsets
245 */
Jeenu Viswambharan32ceef52018-08-02 10:14:12 +0100246#define read_ctx_reg(ctx, offset) ((ctx)->_regs[(offset) >> DWORD_SHIFT])
247#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[(offset) >> DWORD_SHIFT]) \
248 = (uint64_t) (val))
Achin Gupta9ac63c52014-01-16 12:08:03 +0000249
250/*
251 * Top-level context structure which is used by EL3 firmware to
252 * preserve the state of a core at EL1 in one of the two security
253 * states and save enough EL3 meta data to be able to return to that
254 * EL and security state. The context management library will be used
255 * to ensure that SP_EL3 always points to an instance of this
256 * structure at exception entry and exit. Each instance will
257 * correspond to either the secure or the non-secure state.
258 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100259typedef struct cpu_context {
260 gp_regs_t gpregs_ctx;
261 el3_state_t el3state_ctx;
262 el1_sys_regs_t sysregs_ctx;
Juan Castillo258e94f2014-06-25 17:26:36 +0100263#if CTX_INCLUDE_FPREGS
Dan Handleye2712bc2014-04-10 15:37:22 +0100264 fp_regs_t fpregs_ctx;
Juan Castillo258e94f2014-06-25 17:26:36 +0100265#endif
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100266 cve_2018_3639_t cve_2018_3639_ctx;
Dan Handleye2712bc2014-04-10 15:37:22 +0100267} cpu_context_t;
Achin Gupta9ac63c52014-01-16 12:08:03 +0000268
Dan Handleye2712bc2014-04-10 15:37:22 +0100269/* Macros to access members of the 'cpu_context_t' structure */
270#define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx)
Juan Castillo258e94f2014-06-25 17:26:36 +0100271#if CTX_INCLUDE_FPREGS
Dan Handleye2712bc2014-04-10 15:37:22 +0100272#define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx)
Juan Castillo258e94f2014-06-25 17:26:36 +0100273#endif
Dan Handleye2712bc2014-04-10 15:37:22 +0100274#define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx)
275#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx)
Dimitris Papastamosbb1fd5b2018-06-07 11:29:15 +0100276#define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx)
Achin Gupta9ac63c52014-01-16 12:08:03 +0000277
278/*
279 * Compile time assertions related to the 'cpu_context' structure to
280 * ensure that the assembler and the compiler view of the offsets of
281 * the structure members is the same.
282 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100283CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
Achin Gupta07f4e072014-02-02 12:02:23 +0000284 assert_core_context_gp_offset_mismatch);
Dan Handleye2712bc2014-04-10 15:37:22 +0100285CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000286 assert_core_context_sys_offset_mismatch);
Juan Castillo258e94f2014-06-25 17:26:36 +0100287#if CTX_INCLUDE_FPREGS
Dan Handleye2712bc2014-04-10 15:37:22 +0100288CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000289 assert_core_context_fp_offset_mismatch);
Juan Castillo258e94f2014-06-25 17:26:36 +0100290#endif
Dan Handleye2712bc2014-04-10 15:37:22 +0100291CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000292 assert_core_context_el3state_offset_mismatch);
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +0100293CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \
294 assert_core_context_cve_2018_3639_offset_mismatch);
Achin Gupta9ac63c52014-01-16 12:08:03 +0000295
Achin Gupta607084e2014-02-09 18:24:19 +0000296/*
297 * Helper macro to set the general purpose registers that correspond to
298 * parameters in an aapcs_64 call i.e. x0-x7
299 */
300#define set_aapcs_args0(ctx, x0) do { \
301 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
Soby Mathew24ab34f2016-05-03 17:11:42 +0100302 } while (0)
Achin Gupta607084e2014-02-09 18:24:19 +0000303#define set_aapcs_args1(ctx, x0, x1) do { \
304 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \
305 set_aapcs_args0(ctx, x0); \
Soby Mathew24ab34f2016-05-03 17:11:42 +0100306 } while (0)
Achin Gupta607084e2014-02-09 18:24:19 +0000307#define set_aapcs_args2(ctx, x0, x1, x2) do { \
308 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
309 set_aapcs_args1(ctx, x0, x1); \
Soby Mathew24ab34f2016-05-03 17:11:42 +0100310 } while (0)
Achin Gupta607084e2014-02-09 18:24:19 +0000311#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \
312 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \
313 set_aapcs_args2(ctx, x0, x1, x2); \
Soby Mathew24ab34f2016-05-03 17:11:42 +0100314 } while (0)
Achin Gupta607084e2014-02-09 18:24:19 +0000315#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \
316 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \
317 set_aapcs_args3(ctx, x0, x1, x2, x3); \
Soby Mathew24ab34f2016-05-03 17:11:42 +0100318 } while (0)
Achin Gupta607084e2014-02-09 18:24:19 +0000319#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \
320 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
321 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \
Soby Mathew24ab34f2016-05-03 17:11:42 +0100322 } while (0)
Achin Gupta607084e2014-02-09 18:24:19 +0000323#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \
324 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \
325 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
Soby Mathew24ab34f2016-05-03 17:11:42 +0100326 } while (0)
Achin Gupta607084e2014-02-09 18:24:19 +0000327#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \
328 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \
329 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \
Soby Mathew24ab34f2016-05-03 17:11:42 +0100330 } while (0)
Achin Gupta607084e2014-02-09 18:24:19 +0000331
Achin Gupta9ac63c52014-01-16 12:08:03 +0000332/*******************************************************************************
333 * Function prototypes
334 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100335void el1_sysregs_context_save(el1_sys_regs_t *regs);
336void el1_sysregs_context_restore(el1_sys_regs_t *regs);
Juan Castillo258e94f2014-06-25 17:26:36 +0100337#if CTX_INCLUDE_FPREGS
Dan Handleye2712bc2014-04-10 15:37:22 +0100338void fpregs_context_save(fp_regs_t *regs);
339void fpregs_context_restore(fp_regs_t *regs);
Juan Castillo258e94f2014-06-25 17:26:36 +0100340#endif
Achin Gupta9ac63c52014-01-16 12:08:03 +0000341
Soby Mathew5e5c2072014-04-07 15:28:55 +0100342
Achin Gupta9ac63c52014-01-16 12:08:03 +0000343#undef CTX_SYSREG_ALL
Juan Castillo258e94f2014-06-25 17:26:36 +0100344#if CTX_INCLUDE_FPREGS
345#undef CTX_FPREG_ALL
346#endif
Achin Gupta07f4e072014-02-02 12:02:23 +0000347#undef CTX_GPREG_ALL
Achin Gupta9ac63c52014-01-16 12:08:03 +0000348#undef CTX_EL3STATE_ALL
349
350#endif /* __ASSEMBLY__ */
351
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000352#endif /* CONTEXT_H */