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Achin Gupta9ac63c52014-01-16 12:08:03 +00001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __CONTEXT_H__
32#define __CONTEXT_H__
33
34#include <bl_common.h>
35#include <arch.h>
36
37/*******************************************************************************
38 * Constants that allow assembler code to access members of and the 'el3_state'
39 * structure at their correct offsets. Note that some of the registers are only
40 * 32-bits wide but are stored as 64-bit values for convenience
41 ******************************************************************************/
42#define CTX_EL3STATE_OFFSET 0x0
43#define CTX_SAVED_SP_EL3 0x0
44#define CTX_SAVED_SP_EL0 0x8
45#define CTX_SPSR_EL3 0x10
46#define CTX_ELR_EL3 0x18
47#define CTX_SCR_EL3 0x20
48#define CTX_SCTLR_EL3 0x28
49#define CTX_CPTR_EL3 0x30
50/* Unused space to allow registers to be stored as pairs */
51#define CTX_CNTFRQ_EL0 0x40
52#define CTX_MAIR_EL3 0x48
53#define CTX_TCR_EL3 0x50
54#define CTX_TTBR0_EL3 0x58
55#define CTX_DAIF_EL3 0x60
56#define CTX_VBAR_EL3 0x68 /* Currently unused */
57#define CTX_EL3STATE_END 0x70
58
59/*******************************************************************************
60 * Constants that allow assembler code to access members of and the
61 * 'el1_sys_regs' structure at their correct offsets. Note that some of the
62 * registers are only 32-bits wide but are stored as 64-bit values for
63 * convenience
64 ******************************************************************************/
65#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
66#define CTX_SPSR_EL1 0x0
67#define CTX_ELR_EL1 0x8
68#define CTX_SPSR_ABT 0x10
69#define CTX_SPSR_UND 0x18
70#define CTX_SPSR_IRQ 0x20
71#define CTX_SPSR_FIQ 0x28
72#define CTX_SCTLR_EL1 0x30
73#define CTX_ACTLR_EL1 0x38
74#define CTX_CPACR_EL1 0x40
75#define CTX_CSSELR_EL1 0x48
76#define CTX_SP_EL1 0x50
77#define CTX_ESR_EL1 0x58
78#define CTX_TTBR0_EL1 0x60
79#define CTX_TTBR1_EL1 0x68
80#define CTX_MAIR_EL1 0x70
81#define CTX_AMAIR_EL1 0x78
82#define CTX_TCR_EL1 0x80
83#define CTX_TPIDR_EL1 0x88
84#define CTX_TPIDR_EL0 0x90
85#define CTX_TPIDRRO_EL0 0x98
86#define CTX_DACR32_EL2 0xa0
87#define CTX_IFSR32_EL2 0xa8
88#define CTX_PAR_EL1 0xb0
89#define CTX_FAR_EL1 0xb8
90#define CTX_AFSR0_EL1 0xc0
91#define CTX_AFSR1_EL1 0xc8
92#define CTX_CONTEXTIDR_EL1 0xd0
93#define CTX_VBAR_EL1 0xd8
94#define CTX_CNTP_CTL_EL0 0xe0
95#define CTX_CNTP_CVAL_EL0 0xe8
96#define CTX_CNTV_CTL_EL0 0xf0
97#define CTX_CNTV_CVAL_EL0 0xf8
98#define CTX_CNTKCTL_EL1 0x100
99#define CTX_FP_FPEXC32_EL2 0x108
100#define CTX_SYSREGS_END 0x110
101
102/*******************************************************************************
103 * Constants that allow assembler code to access members of and the 'fp_regs'
104 * structure at their correct offsets.
105 ******************************************************************************/
106#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END)
107#define CTX_FP_Q0 0x0
108#define CTX_FP_Q1 0x10
109#define CTX_FP_Q2 0x20
110#define CTX_FP_Q3 0x30
111#define CTX_FP_Q4 0x40
112#define CTX_FP_Q5 0x50
113#define CTX_FP_Q6 0x60
114#define CTX_FP_Q7 0x70
115#define CTX_FP_Q8 0x80
116#define CTX_FP_Q9 0x90
117#define CTX_FP_Q10 0xa0
118#define CTX_FP_Q11 0xb0
119#define CTX_FP_Q12 0xc0
120#define CTX_FP_Q13 0xd0
121#define CTX_FP_Q14 0xe0
122#define CTX_FP_Q15 0xf0
123#define CTX_FP_Q16 0x100
124#define CTX_FP_Q17 0x110
125#define CTX_FP_Q18 0x120
126#define CTX_FP_Q19 0x130
127#define CTX_FP_Q20 0x140
128#define CTX_FP_Q21 0x150
129#define CTX_FP_Q22 0x160
130#define CTX_FP_Q23 0x170
131#define CTX_FP_Q24 0x180
132#define CTX_FP_Q25 0x190
133#define CTX_FP_Q26 0x1a0
134#define CTX_FP_Q27 0x1b0
135#define CTX_FP_Q28 0x1c0
136#define CTX_FP_Q29 0x1d0
137#define CTX_FP_Q30 0x1e0
138#define CTX_FP_Q31 0x1f0
139#define CTX_FP_FPSR 0x200
140#define CTX_FP_FPCR 0x208
141#define CTX_FPREGS_END 0x210
142
143#ifndef __ASSEMBLY__
144
145/*
146 * Common constants to help define the 'cpu_context' structure and its
147 * members below.
148 */
149#define DWORD_SHIFT 3
150#define DEFINE_REG_STRUCT(name, num_regs) \
151 typedef struct { \
152 uint64_t _regs[num_regs]; \
153 } __aligned(16) name
154
155/* Constants to determine the size of individual context structures */
156#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT)
157#define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT)
158#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT)
159
160/*
161 * AArch64 EL1 system register context structure for preserving the
162 * architectural state during switches from one security state to
163 * another in EL1.
164 */
165DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL);
166
167/*
168 * AArch64 floating point register context structure for preserving
169 * the floating point state during switches from one security state to
170 * another.
171 */
172DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL);
173
174/*
175 * Miscellaneous registers used by EL3 firmware to maintain its state
176 * across exception entries and exits
177 */
178DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL);
179
180/*
181 * Macros to access members of any of the above structures using their
182 * offsets
183 */
184#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT])
185#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \
186 = val)
187
188/*
189 * Top-level context structure which is used by EL3 firmware to
190 * preserve the state of a core at EL1 in one of the two security
191 * states and save enough EL3 meta data to be able to return to that
192 * EL and security state. The context management library will be used
193 * to ensure that SP_EL3 always points to an instance of this
194 * structure at exception entry and exit. Each instance will
195 * correspond to either the secure or the non-secure state.
196 */
197typedef struct {
198 el3_state el3state_ctx;
199 el1_sys_regs sysregs_ctx;
200 fp_regs fpregs_ctx;
201} cpu_context;
202
203/* Macros to access members of the 'cpu_context' structure */
204#define get_el3state_ctx(h) (&((cpu_context *) h)->el3state_ctx)
205#define get_fpregs_ctx(h) (&((cpu_context *) h)->fpregs_ctx)
206#define get_sysregs_ctx(h) (&((cpu_context *) h)->sysregs_ctx)
207
208/*
209 * Compile time assertions related to the 'cpu_context' structure to
210 * ensure that the assembler and the compiler view of the offsets of
211 * the structure members is the same.
212 */
213CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context, sysregs_ctx), \
214 assert_core_context_sys_offset_mismatch);
215CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context, fpregs_ctx), \
216 assert_core_context_fp_offset_mismatch);
217CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context, el3state_ctx), \
218 assert_core_context_el3state_offset_mismatch);
219
220/*******************************************************************************
221 * Function prototypes
222 ******************************************************************************/
223void el3_sysregs_context_save(el3_state *regs);
224void el3_sysregs_context_restore(el3_state *regs);
225void el1_sysregs_context_save(el1_sys_regs *regs);
226void el1_sysregs_context_restore(el1_sys_regs *regs);
227void fpregs_context_save(fp_regs *regs);
228void fpregs_context_restore(fp_regs *regs);
229
230#undef CTX_SYSREG_ALL
231#undef CTX_FP_ALL
232#undef CTX_EL3STATE_ALL
233
234#endif /* __ASSEMBLY__ */
235
236#endif /* __CONTEXT_H__ */