include: add U()/ULL() macros for constants
This patch uses the U() and ULL() macros for constants, to fix some
of the signed-ness defects flagged by the MISRA scanner.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index a2ae897..dead971 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,40 +11,40 @@
* Constants that allow assembler code to access members of and the 'gp_regs'
* structure at their correct offsets.
******************************************************************************/
-#define CTX_GPREGS_OFFSET 0x0
-#define CTX_GPREG_X0 0x0
-#define CTX_GPREG_X1 0x8
-#define CTX_GPREG_X2 0x10
-#define CTX_GPREG_X3 0x18
-#define CTX_GPREG_X4 0x20
-#define CTX_GPREG_X5 0x28
-#define CTX_GPREG_X6 0x30
-#define CTX_GPREG_X7 0x38
-#define CTX_GPREG_X8 0x40
-#define CTX_GPREG_X9 0x48
-#define CTX_GPREG_X10 0x50
-#define CTX_GPREG_X11 0x58
-#define CTX_GPREG_X12 0x60
-#define CTX_GPREG_X13 0x68
-#define CTX_GPREG_X14 0x70
-#define CTX_GPREG_X15 0x78
-#define CTX_GPREG_X16 0x80
-#define CTX_GPREG_X17 0x88
-#define CTX_GPREG_X18 0x90
-#define CTX_GPREG_X19 0x98
-#define CTX_GPREG_X20 0xa0
-#define CTX_GPREG_X21 0xa8
-#define CTX_GPREG_X22 0xb0
-#define CTX_GPREG_X23 0xb8
-#define CTX_GPREG_X24 0xc0
-#define CTX_GPREG_X25 0xc8
-#define CTX_GPREG_X26 0xd0
-#define CTX_GPREG_X27 0xd8
-#define CTX_GPREG_X28 0xe0
-#define CTX_GPREG_X29 0xe8
-#define CTX_GPREG_LR 0xf0
-#define CTX_GPREG_SP_EL0 0xf8
-#define CTX_GPREGS_END 0x100
+#define CTX_GPREGS_OFFSET U(0x0)
+#define CTX_GPREG_X0 U(0x0)
+#define CTX_GPREG_X1 U(0x8)
+#define CTX_GPREG_X2 U(0x10)
+#define CTX_GPREG_X3 U(0x18)
+#define CTX_GPREG_X4 U(0x20)
+#define CTX_GPREG_X5 U(0x28)
+#define CTX_GPREG_X6 U(0x30)
+#define CTX_GPREG_X7 U(0x38)
+#define CTX_GPREG_X8 U(0x40)
+#define CTX_GPREG_X9 U(0x48)
+#define CTX_GPREG_X10 U(0x50)
+#define CTX_GPREG_X11 U(0x58)
+#define CTX_GPREG_X12 U(0x60)
+#define CTX_GPREG_X13 U(0x68)
+#define CTX_GPREG_X14 U(0x70)
+#define CTX_GPREG_X15 U(0x78)
+#define CTX_GPREG_X16 U(0x80)
+#define CTX_GPREG_X17 U(0x88)
+#define CTX_GPREG_X18 U(0x90)
+#define CTX_GPREG_X19 U(0x98)
+#define CTX_GPREG_X20 U(0xa0)
+#define CTX_GPREG_X21 U(0xa8)
+#define CTX_GPREG_X22 U(0xb0)
+#define CTX_GPREG_X23 U(0xb8)
+#define CTX_GPREG_X24 U(0xc0)
+#define CTX_GPREG_X25 U(0xc8)
+#define CTX_GPREG_X26 U(0xd0)
+#define CTX_GPREG_X27 U(0xd8)
+#define CTX_GPREG_X28 U(0xe0)
+#define CTX_GPREG_X29 U(0xe8)
+#define CTX_GPREG_LR U(0xf0)
+#define CTX_GPREG_SP_EL0 U(0xf8)
+#define CTX_GPREGS_END U(0x100)
/*******************************************************************************
* Constants that allow assembler code to access members of and the 'el3_state'
@@ -52,11 +52,11 @@
* 32-bits wide but are stored as 64-bit values for convenience
******************************************************************************/
#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
-#define CTX_SCR_EL3 0x0
-#define CTX_RUNTIME_SP 0x8
-#define CTX_SPSR_EL3 0x10
-#define CTX_ELR_EL3 0x18
-#define CTX_EL3STATE_END 0x20
+#define CTX_SCR_EL3 U(0x0)
+#define CTX_RUNTIME_SP U(0x8)
+#define CTX_SPSR_EL3 U(0x10)
+#define CTX_ELR_EL3 U(0x18)
+#define CTX_EL3STATE_END U(0x20)
/*******************************************************************************
* Constants that allow assembler code to access members of and the
@@ -65,44 +65,44 @@
* convenience
******************************************************************************/
#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
-#define CTX_SPSR_EL1 0x0
-#define CTX_ELR_EL1 0x8
-#define CTX_SCTLR_EL1 0x10
-#define CTX_ACTLR_EL1 0x18
-#define CTX_CPACR_EL1 0x20
-#define CTX_CSSELR_EL1 0x28
-#define CTX_SP_EL1 0x30
-#define CTX_ESR_EL1 0x38
-#define CTX_TTBR0_EL1 0x40
-#define CTX_TTBR1_EL1 0x48
-#define CTX_MAIR_EL1 0x50
-#define CTX_AMAIR_EL1 0x58
-#define CTX_TCR_EL1 0x60
-#define CTX_TPIDR_EL1 0x68
-#define CTX_TPIDR_EL0 0x70
-#define CTX_TPIDRRO_EL0 0x78
-#define CTX_PAR_EL1 0x80
-#define CTX_FAR_EL1 0x88
-#define CTX_AFSR0_EL1 0x90
-#define CTX_AFSR1_EL1 0x98
-#define CTX_CONTEXTIDR_EL1 0xa0
-#define CTX_VBAR_EL1 0xa8
+#define CTX_SPSR_EL1 U(0x0)
+#define CTX_ELR_EL1 U(0x8)
+#define CTX_SCTLR_EL1 U(0x10)
+#define CTX_ACTLR_EL1 U(0x18)
+#define CTX_CPACR_EL1 U(0x20)
+#define CTX_CSSELR_EL1 U(0x28)
+#define CTX_SP_EL1 U(0x30)
+#define CTX_ESR_EL1 U(0x38)
+#define CTX_TTBR0_EL1 U(0x40)
+#define CTX_TTBR1_EL1 U(0x48)
+#define CTX_MAIR_EL1 U(0x50)
+#define CTX_AMAIR_EL1 U(0x58)
+#define CTX_TCR_EL1 U(0x60)
+#define CTX_TPIDR_EL1 U(0x68)
+#define CTX_TPIDR_EL0 U(0x70)
+#define CTX_TPIDRRO_EL0 U(0x78)
+#define CTX_PAR_EL1 U(0x80)
+#define CTX_FAR_EL1 U(0x88)
+#define CTX_AFSR0_EL1 U(0x90)
+#define CTX_AFSR1_EL1 U(0x98)
+#define CTX_CONTEXTIDR_EL1 U(0xa0)
+#define CTX_VBAR_EL1 U(0xa8)
/*
* If the platform is AArch64-only, there is no need to save and restore these
* AArch32 registers.
*/
#if CTX_INCLUDE_AARCH32_REGS
-#define CTX_SPSR_ABT 0xb0
-#define CTX_SPSR_UND 0xb8
-#define CTX_SPSR_IRQ 0xc0
-#define CTX_SPSR_FIQ 0xc8
-#define CTX_DACR32_EL2 0xd0
-#define CTX_IFSR32_EL2 0xd8
-#define CTX_FP_FPEXC32_EL2 0xe0
-#define CTX_TIMER_SYSREGS_OFF 0xf0 /* Align to the next 16 byte boundary */
+#define CTX_SPSR_ABT U(0xb0)
+#define CTX_SPSR_UND U(0xb8)
+#define CTX_SPSR_IRQ U(0xc0)
+#define CTX_SPSR_FIQ U(0xc8)
+#define CTX_DACR32_EL2 U(0xd0)
+#define CTX_IFSR32_EL2 U(0xd8)
+#define CTX_FP_FPEXC32_EL2 U(0xe0)
+#define CTX_TIMER_SYSREGS_OFF U(0xf0) /* Align to the next 16 byte boundary */
#else
-#define CTX_TIMER_SYSREGS_OFF 0xb0
+#define CTX_TIMER_SYSREGS_OFF U(0xb0)
#endif /* __CTX_INCLUDE_AARCH32_REGS__ */
/*
@@ -110,12 +110,12 @@
* space for them in the context
*/
#if NS_TIMER_SWITCH
-#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x0)
-#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x8)
-#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x10)
-#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x18)
-#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + 0x20)
-#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + 0x30) /* Align to the next 16 byte boundary */
+#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x0))
+#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x8))
+#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x10))
+#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x18))
+#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + U(0x20))
+#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + U(0x30)) /* Align to the next 16 byte boundary */
#else
#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF
#endif /* __NS_TIMER_SWITCH__ */
@@ -126,41 +126,41 @@
******************************************************************************/
#if CTX_INCLUDE_FPREGS
#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END)
-#define CTX_FP_Q0 0x0
-#define CTX_FP_Q1 0x10
-#define CTX_FP_Q2 0x20
-#define CTX_FP_Q3 0x30
-#define CTX_FP_Q4 0x40
-#define CTX_FP_Q5 0x50
-#define CTX_FP_Q6 0x60
-#define CTX_FP_Q7 0x70
-#define CTX_FP_Q8 0x80
-#define CTX_FP_Q9 0x90
-#define CTX_FP_Q10 0xa0
-#define CTX_FP_Q11 0xb0
-#define CTX_FP_Q12 0xc0
-#define CTX_FP_Q13 0xd0
-#define CTX_FP_Q14 0xe0
-#define CTX_FP_Q15 0xf0
-#define CTX_FP_Q16 0x100
-#define CTX_FP_Q17 0x110
-#define CTX_FP_Q18 0x120
-#define CTX_FP_Q19 0x130
-#define CTX_FP_Q20 0x140
-#define CTX_FP_Q21 0x150
-#define CTX_FP_Q22 0x160
-#define CTX_FP_Q23 0x170
-#define CTX_FP_Q24 0x180
-#define CTX_FP_Q25 0x190
-#define CTX_FP_Q26 0x1a0
-#define CTX_FP_Q27 0x1b0
-#define CTX_FP_Q28 0x1c0
-#define CTX_FP_Q29 0x1d0
-#define CTX_FP_Q30 0x1e0
-#define CTX_FP_Q31 0x1f0
-#define CTX_FP_FPSR 0x200
-#define CTX_FP_FPCR 0x208
-#define CTX_FPREGS_END 0x210
+#define CTX_FP_Q0 U(0x0)
+#define CTX_FP_Q1 U(0x10)
+#define CTX_FP_Q2 U(0x20)
+#define CTX_FP_Q3 U(0x30)
+#define CTX_FP_Q4 U(0x40)
+#define CTX_FP_Q5 U(0x50)
+#define CTX_FP_Q6 U(0x60)
+#define CTX_FP_Q7 U(0x70)
+#define CTX_FP_Q8 U(0x80)
+#define CTX_FP_Q9 U(0x90)
+#define CTX_FP_Q10 U(0xa0)
+#define CTX_FP_Q11 U(0xb0)
+#define CTX_FP_Q12 U(0xc0)
+#define CTX_FP_Q13 U(0xd0)
+#define CTX_FP_Q14 U(0xe0)
+#define CTX_FP_Q15 U(0xf0)
+#define CTX_FP_Q16 U(0x100)
+#define CTX_FP_Q17 U(0x110)
+#define CTX_FP_Q18 U(0x120)
+#define CTX_FP_Q19 U(0x130)
+#define CTX_FP_Q20 U(0x140)
+#define CTX_FP_Q21 U(0x150)
+#define CTX_FP_Q22 U(0x160)
+#define CTX_FP_Q23 U(0x170)
+#define CTX_FP_Q24 U(0x180)
+#define CTX_FP_Q25 U(0x190)
+#define CTX_FP_Q26 U(0x1a0)
+#define CTX_FP_Q27 U(0x1b0)
+#define CTX_FP_Q28 U(0x1c0)
+#define CTX_FP_Q29 U(0x1d0)
+#define CTX_FP_Q30 U(0x1e0)
+#define CTX_FP_Q31 U(0x1f0)
+#define CTX_FP_FPSR U(0x200)
+#define CTX_FP_FPCR U(0x208)
+#define CTX_FPREGS_END U(0x210)
#endif
#ifndef __ASSEMBLY__
@@ -173,7 +173,7 @@
* Common constants to help define the 'cpu_context' structure and its
* members below.
*/
-#define DWORD_SHIFT 3
+#define DWORD_SHIFT U(3)
#define DEFINE_REG_STRUCT(name, num_regs) \
typedef struct name { \
uint64_t _regs[num_regs]; \