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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Vikram Kanigirifbb13012016-02-15 11:54:14 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2b6b5742015-03-19 19:17:53 +00007#include <plat_arm.h>
Dan Handleyed6ff952014-05-14 17:44:19 +01008#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010010#if LOAD_IMAGE_V2
11void bl31_early_platform_setup(void *from_bl2,
12 void *plat_params_from_bl2)
13#else
Vikram Kanigirida567432014-04-15 18:08:08 +010014void bl31_early_platform_setup(bl31_params_t *from_bl2,
Vikram Kanigirid8c9d262014-05-16 18:48:12 +010015 void *plat_params_from_bl2)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010016#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010017{
Dan Handley2b6b5742015-03-19 19:17:53 +000018 arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);
Vikram Kanigiri3684abf2014-03-27 14:33:15 +000019
Achin Gupta4f6ad662013-10-25 09:08:21 +010020 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +010021 fvp_config_setup();
Vikram Kanigiri96377452014-04-24 11:02:16 +010022
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +010023 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000024 * Initialize the correct interconnect for this cluster during cold
25 * boot. No need for locks as no other CPU is active.
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +010026 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000027 fvp_interconnect_init();
Sandrine Bailleuxda797f62015-05-14 14:13:05 +010028
Dan Handley2b6b5742015-03-19 19:17:53 +000029 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000030 * Enable coherency in interconnect for the primary CPU's cluster.
Sandrine Bailleuxda797f62015-05-14 14:13:05 +010031 * Earlier bootloader stages might already do this (e.g. Trusted
32 * Firmware's BL1 does it) but we can't assume so. There is no harm in
33 * executing this code twice anyway.
Dan Handley2b6b5742015-03-19 19:17:53 +000034 * FVP PSCI code will enable coherency for other clusters.
35 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000036 fvp_interconnect_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +010037}