Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 1 | /* |
Manish V Badarkhe | dd6f252 | 2021-02-22 17:30:17 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <drivers/arm/tzc400.h> |
| 11 | #include <lib/utils_def.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 12 | #include <plat/arm/board/common/v2m_def.h> |
| 13 | #include <plat/arm/common/arm_def.h> |
| 14 | #include <plat/arm/common/arm_spm_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <plat/common/common_def.h> |
| 16 | |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 17 | #include "../fvp_def.h" |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 18 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 19 | /* Required platform porting definitions */ |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 20 | #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ |
| 21 | U(FVP_MAX_CPUS_PER_CLUSTER) * \ |
| 22 | U(FVP_MAX_PE_PER_CPU)) |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 23 | |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 24 | #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ |
| 25 | PLATFORM_CORE_COUNT + U(1)) |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 26 | |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 27 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 28 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 29 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 30 | * Other platform porting definitions are provided by included headers |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 31 | */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 32 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 33 | /* |
| 34 | * Required ARM standard platform porting definitions |
| 35 | */ |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 36 | #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 37 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 38 | #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 39 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 40 | #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) |
| 41 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 42 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 43 | #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) |
| 44 | #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 45 | |
Arunachalam Ganapathy | 40618cf | 2020-07-27 13:51:30 +0100 | [diff] [blame] | 46 | /* |
| 47 | * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to |
| 48 | * max size of BL32 image. |
| 49 | */ |
| 50 | #if defined(SPD_spmd) |
| 51 | #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 52 | #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ |
| 53 | #endif |
| 54 | |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 55 | /* virtual address used by dynamic mem_protect for chunk_base */ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 56 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 57 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 58 | /* No SCP in FVP */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 59 | #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 60 | |
Sami Mujawar | a43ae7c | 2019-05-09 13:35:02 +0100 | [diff] [blame] | 61 | #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 62 | #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 63 | |
Madhukar Pappireddy | aa1121f | 2020-03-13 13:00:17 -0500 | [diff] [blame] | 64 | #define PLAT_HW_CONFIG_DTB_BASE ULL(0x82000000) |
| 65 | #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) |
| 66 | |
| 67 | #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ |
| 68 | PLAT_HW_CONFIG_DTB_BASE, \ |
| 69 | PLAT_HW_CONFIG_DTB_SIZE, \ |
| 70 | MT_MEMORY | MT_RO | MT_NS) |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 71 | /* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 72 | * Load address of BL33 for this platform port |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 73 | */ |
Sandrine Bailleux | afa91db | 2019-01-31 15:01:32 +0100 | [diff] [blame] | 74 | #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 75 | |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 76 | /* |
| 77 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 78 | * plat_arm_mmap array defined for each BL stage. |
| 79 | */ |
| 80 | #if defined(IMAGE_BL31) |
Paul Beesley | db4e25a | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 81 | # if SPM_MM |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 82 | # define PLAT_ARM_MMAP_ENTRIES 10 |
Antonio Nino Diaz | 840627f | 2018-11-27 08:36:02 +0000 | [diff] [blame] | 83 | # define MAX_XLAT_TABLES 9 |
| 84 | # define PLAT_SP_IMAGE_MMAP_REGIONS 30 |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 85 | # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 |
| 86 | # else |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 87 | # define PLAT_ARM_MMAP_ENTRIES 9 |
Ambroise Vincent | 9660dc1 | 2019-07-12 13:47:03 +0100 | [diff] [blame] | 88 | # if USE_DEBUGFS |
Madhukar Pappireddy | aa1121f | 2020-03-13 13:00:17 -0500 | [diff] [blame] | 89 | # define MAX_XLAT_TABLES 8 |
Ambroise Vincent | 9660dc1 | 2019-07-12 13:47:03 +0100 | [diff] [blame] | 90 | # else |
Madhukar Pappireddy | aa1121f | 2020-03-13 13:00:17 -0500 | [diff] [blame] | 91 | # define MAX_XLAT_TABLES 7 |
Ambroise Vincent | 9660dc1 | 2019-07-12 13:47:03 +0100 | [diff] [blame] | 92 | # endif |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 93 | # endif |
| 94 | #elif defined(IMAGE_BL32) |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 95 | # define PLAT_ARM_MMAP_ENTRIES 9 |
Madhukar Pappireddy | aa1121f | 2020-03-13 13:00:17 -0500 | [diff] [blame] | 96 | # define MAX_XLAT_TABLES 6 |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 97 | #elif !USE_ROMLIB |
| 98 | # define PLAT_ARM_MMAP_ENTRIES 11 |
| 99 | # define MAX_XLAT_TABLES 5 |
| 100 | #else |
| 101 | # define PLAT_ARM_MMAP_ENTRIES 12 |
| 102 | # define MAX_XLAT_TABLES 6 |
| 103 | #endif |
| 104 | |
| 105 | /* |
| 106 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 107 | * plus a little space for growth. |
| 108 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 109 | #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 110 | |
| 111 | /* |
| 112 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 113 | */ |
| 114 | |
| 115 | #if USE_ROMLIB |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 116 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) |
| 117 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) |
Manish V Badarkhe | dd6f252 | 2021-02-22 17:30:17 +0000 | [diff] [blame] | 118 | #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 119 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 120 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) |
| 121 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 122 | #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 123 | #endif |
| 124 | |
| 125 | /* |
| 126 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 127 | * little space for growth. |
| 128 | */ |
| 129 | #if TRUSTED_BOARD_BOOT |
Manish V Badarkhe | b92a954 | 2020-09-04 15:01:30 +0100 | [diff] [blame] | 130 | #if COT_DESC_IN_DTB |
| 131 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) |
| 132 | #else |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 133 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) |
Manish V Badarkhe | b92a954 | 2020-09-04 15:01:30 +0100 | [diff] [blame] | 134 | #endif |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 135 | #else |
Manish V Badarkhe | 1856cc9 | 2020-07-10 09:44:21 +0100 | [diff] [blame] | 136 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 137 | #endif |
| 138 | |
Alexei Fedorov | ea0424f | 2020-02-17 13:38:35 +0000 | [diff] [blame] | 139 | #if RESET_TO_BL31 |
| 140 | /* Size of Trusted SRAM - the first 4KB of shared memory */ |
| 141 | #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
| 142 | ARM_SHARED_RAM_SIZE) |
| 143 | #else |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 144 | /* |
| 145 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 146 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 147 | * BL2 and BL1-RW |
| 148 | */ |
Manish V Badarkhe | fbf1fd2 | 2020-06-09 11:31:17 +0100 | [diff] [blame] | 149 | #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) |
Alexei Fedorov | ea0424f | 2020-02-17 13:38:35 +0000 | [diff] [blame] | 150 | #endif /* RESET_TO_BL31 */ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 151 | |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 152 | #ifndef __aarch64__ |
Manish Pandey | 928da86 | 2021-06-10 15:22:48 +0100 | [diff] [blame] | 153 | #if RESET_TO_SP_MIN |
| 154 | /* Size of Trusted SRAM - the first 4KB of shared memory */ |
| 155 | #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
| 156 | ARM_SHARED_RAM_SIZE) |
| 157 | #else |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 158 | /* |
| 159 | * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is |
| 160 | * calculated using the current SP_MIN PROGBITS debug size plus the sizes of |
| 161 | * BL2 and BL1-RW |
| 162 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 163 | # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) |
Manish Pandey | 928da86 | 2021-06-10 15:22:48 +0100 | [diff] [blame] | 164 | #endif /* RESET_TO_SP_MIN */ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 165 | #endif |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 166 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 167 | /* |
| 168 | * Size of cacheable stacks |
| 169 | */ |
| 170 | #if defined(IMAGE_BL1) |
| 171 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 172 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 173 | # else |
Louis Mayencourt | 2cef2d3 | 2020-01-17 16:10:45 +0000 | [diff] [blame] | 174 | # define PLATFORM_STACK_SIZE UL(0x500) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 175 | # endif |
| 176 | #elif defined(IMAGE_BL2) |
| 177 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 178 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 179 | # else |
Louis Mayencourt | 2cef2d3 | 2020-01-17 16:10:45 +0000 | [diff] [blame] | 180 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 181 | # endif |
| 182 | #elif defined(IMAGE_BL2U) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 183 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 184 | #elif defined(IMAGE_BL31) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 185 | # define PLATFORM_STACK_SIZE UL(0x800) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 186 | #elif defined(IMAGE_BL32) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 187 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 188 | #endif |
| 189 | |
| 190 | #define MAX_IO_DEVICES 3 |
| 191 | #define MAX_IO_HANDLES 4 |
| 192 | |
| 193 | /* Reserve the last block of flash for PSCI MEM PROTECT flag */ |
Manish V Badarkhe | 443ccbc | 2021-04-22 11:13:21 +0100 | [diff] [blame] | 194 | #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE |
| 195 | #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 196 | |
Manish V Badarkhe | dd6f252 | 2021-02-22 17:30:17 +0000 | [diff] [blame] | 197 | #if ARM_GPT_SUPPORT |
| 198 | /* |
| 199 | * Offset of the FIP in the GPT image. BL1 component uses this option |
| 200 | * as it does not load the partition table to get the FIP base |
| 201 | * address. At sector 34 by default (i.e. after reserved sectors 0-33) |
| 202 | * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 |
| 203 | */ |
| 204 | #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 |
| 205 | #endif /* ARM_GPT_SUPPORT */ |
| 206 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 207 | #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE |
| 208 | #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 209 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 210 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 211 | * PL011 related constants |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 212 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 213 | #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE |
| 214 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 215 | |
Usama Arif | 81eb5ce | 2019-02-11 16:35:42 +0000 | [diff] [blame] | 216 | #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE |
| 217 | #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 218 | |
Usama Arif | 81eb5ce | 2019-02-11 16:35:42 +0000 | [diff] [blame] | 219 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE |
| 220 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 221 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 222 | #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE |
| 223 | #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 224 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 225 | #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 226 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 227 | /* CCI related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 228 | #define PLAT_FVP_CCI400_BASE UL(0x2c090000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 229 | #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 |
| 230 | #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 |
| 231 | |
| 232 | /* CCI-500/CCI-550 on Base platform */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 233 | #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 234 | #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 |
| 235 | #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 |
Juan Castillo | e33ee5f | 2014-12-19 09:51:00 +0000 | [diff] [blame] | 236 | |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 237 | /* CCN related constants. Only CCN 502 is currently supported */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 238 | #define PLAT_ARM_CCN_BASE UL(0x2e000000) |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 239 | #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 |
| 240 | |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 241 | /* System timer related constants */ |
Antonio Nino Diaz | 6971f00 | 2018-11-06 13:14:21 +0000 | [diff] [blame] | 242 | #define PLAT_ARM_NSTIMER_FRAME_ID U(1) |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 243 | |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 244 | /* Mailbox base address */ |
| 245 | #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE |
| 246 | |
| 247 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 248 | /* TrustZone controller related constants |
| 249 | * |
| 250 | * Currently only filters 0 and 2 are connected on Base FVP. |
| 251 | * Filter 0 : CPU clusters (no access to DRAM by default) |
| 252 | * Filter 1 : not connected |
| 253 | * Filter 2 : LCDs (access to VRAM allowed by default) |
| 254 | * Filter 3 : not connected |
| 255 | * Programming unconnected filters will have no effect at the |
| 256 | * moment. These filter could, however, be connected in future. |
| 257 | * So care should be taken not to configure the unused filters. |
| 258 | * |
| 259 | * Allow only non-secure access to all DRAM to supported devices. |
| 260 | * Give access to the CPUs and Virtio. Some devices |
| 261 | * would normally use the default ID so allow that too. |
| 262 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 263 | #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) |
Soby Mathew | 9c708b5 | 2016-02-26 14:23:19 +0000 | [diff] [blame] | 264 | #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 265 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 266 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 267 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ |
| 268 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ |
| 269 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ |
| 270 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ |
| 271 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 272 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 273 | /* |
| 274 | * GIC related constants to cater for both GICv2 and GICv3 instances of an |
Alexei Fedorov | 61369a2 | 2020-07-13 14:59:02 +0100 | [diff] [blame] | 275 | * FVP. They could be overridden at runtime in case the FVP implements the |
| 276 | * legacy VE memory map. |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 277 | */ |
| 278 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 279 | #define PLAT_ARM_GICR_BASE BASE_GICR_BASE |
| 280 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 281 | |
| 282 | /* |
| 283 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 284 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 285 | * as Group 0 interrupts. |
| 286 | */ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 287 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 288 | ARM_G1S_IRQ_PROPS(grp), \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 289 | INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 290 | GIC_INTR_CFG_LEVEL), \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 291 | INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 292 | GIC_INTR_CFG_LEVEL) |
| 293 | |
| 294 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 295 | |
Balint Dobszay | d0dbd5e | 2019-12-18 15:28:00 +0100 | [diff] [blame] | 296 | #if SDEI_IN_FCONF |
| 297 | #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT |
| 298 | #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT |
| 299 | #else |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 300 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS |
| 301 | #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS |
Balint Dobszay | d0dbd5e | 2019-12-18 15:28:00 +0100 | [diff] [blame] | 302 | #endif |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 303 | |
Ard Biesheuvel | 8b034fc | 2018-12-29 19:43:21 +0100 | [diff] [blame] | 304 | #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ |
| 305 | PLAT_SP_IMAGE_NS_BUF_SIZE) |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 306 | |
Sughosh Ganu | d284b57 | 2018-11-14 10:42:46 +0530 | [diff] [blame] | 307 | #define PLAT_SP_PRI PLAT_RAS_PRI |
| 308 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 309 | /* |
| 310 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 311 | */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 312 | #ifdef __aarch64__ |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 313 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 314 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
| 315 | #else |
| 316 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 317 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 318 | #endif |
| 319 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 320 | #endif /* PLATFORM_DEF_H */ |