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Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06002# Copyright (c) 2016-2023, Arm Limited. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010013# Use T32 by default
14AARCH32_INSTRUCTION_SET := T32
15
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010016# The AArch32 Secure Payload to be built as BL32 image
17AARCH32_SP := none
18
19# The Target build architecture. Supported values are: aarch64, aarch32.
20ARCH := aarch64
21
Alexei Fedorov132e6652020-12-07 16:38:53 +000022# ARM Architecture feature modifiers: none by default
23ARM_ARCH_FEATURE := none
24
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000025# ARM Architecture major and minor versions: 8.0 by default.
26ARM_ARCH_MAJOR := 8
27ARM_ARCH_MINOR := 0
28
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010029# Base commit to perform code check on
30BASE_COMMIT := origin/master
31
Roberto Vargase0e99462017-10-30 14:43:43 +000032# Execute BL2 at EL3
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060033RESET_TO_BL2 := 0
Roberto Vargase0e99462017-10-30 14:43:43 +000034
Balint Dobszay719ba9c2021-03-26 16:23:18 +010035# Only use SP packages if SP layout JSON is defined
36BL2_ENABLE_SP_LOAD := 0
37
Jiafei Pan43a7bf42018-03-21 07:20:09 +000038# BL2 image is stored in XIP memory, for now, this option is only supported
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060039# when RESET_TO_BL2 is 1.
Jiafei Pan43a7bf42018-03-21 07:20:09 +000040BL2_IN_XIP_MEM := 0
41
Hadi Asyrafi461f8f42019-08-20 15:33:27 +080042# Do dcache invalidate upon BL2 entry at EL3
43BL2_INV_DCACHE := 1
44
Alexei Fedorov90f2e882019-05-24 12:17:09 +010045# Select the branch protection features to use.
46BRANCH_PROTECTION := 0
47
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010048# By default, consider that the platform may release several CPUs out of reset.
49# The platform Makefile is free to override this value.
50COLD_BOOT_SINGLE_CPU := 0
51
Julius Wernerb624ae02017-06-09 15:17:15 -070052# Flag to compile in coreboot support code. Exclude by default. The coreboot
53# Makefile system will set this when compiling TF as part of a coreboot image.
54COREBOOT := 0
55
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010056# For Chain of Trust
57CREATE_KEYS := 1
58
59# Build flag to include AArch32 registers in cpu context save and restore during
60# world switch. This flag must be set to 0 for AArch64-only platforms.
61CTX_INCLUDE_AARCH32_REGS := 1
62
63# Include FP registers in cpu context
64CTX_INCLUDE_FPREGS := 0
65
Antonio Nino Diaz594811b2019-01-31 11:58:00 +000066# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
67# must be set to 1 if the platform wants to use this feature in the Secure
68# world. It is not needed to use it in the Non-secure world.
69CTX_INCLUDE_PAUTH_REGS := 0
70
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +010071# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
72# This must be set to 1 if architecture implements Nested Virtualization
73# Extension and platform wants to use this feature in the Secure world
74CTX_INCLUDE_NEVE_REGS := 0
75
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010076# Debug build
77DEBUG := 0
78
Sumit Garg392e4df2019-11-15 10:43:00 +053079# By default disable authenticated decryption support.
80DECRYPTION_SUPPORT := none
81
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010082# Build platform
83DEFAULT_PLAT := fvp
84
Christoph Müllner4f088e42019-04-24 09:45:30 +020085# Disable the generation of the binary image (ELF only).
86DISABLE_BIN_GENERATION := 0
87
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +000088# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards
89# compatibility.
90DISABLE_MTPMU := 0
91
Soby Mathew9fe88042018-03-26 12:43:37 +010092# Enable capability to disable authentication dynamically. Only meant for
93# development platforms.
94DYN_DISABLE_AUTH := 0
95
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +010096# Build option to enable MPAM for lower ELs
97ENABLE_MPAM_FOR_LOWER_ELS := 0
98
Chris Kay03be39d2021-05-05 13:38:30 +010099# Enable the Maximum Power Mitigation Mechanism on supporting cores.
100ENABLE_MPMM := 0
101
102# Enable MPMM configuration via FCONF.
103ENABLE_MPMM_FCONF := 0
104
Soby Mathew078f1a42018-08-28 11:13:55 +0100105# Flag to Enable Position Independant support (PIE)
106ENABLE_PIE := 0
107
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100108# Flag to enable Performance Measurement Framework
109ENABLE_PMF := 0
110
111# Flag to enable PSCI STATs functionality
112ENABLE_PSCI_STAT := 0
113
Zelalem Aweke4d37db82021-07-11 18:33:20 -0500114# Flag to enable Realm Management Extension (FEAT_RME)
115ENABLE_RME := 0
116
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100117# Flag to enable runtime instrumentation using PMF
118ENABLE_RUNTIME_INSTRUMENTATION := 0
119
Douglas Raillard306593d2017-02-24 18:14:15 +0000120# Flag to enable stack corruption protection
121ENABLE_STACK_PROTECTOR := 0
122
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100123# Flag to enable exception handling in EL3
124EL3_EXCEPTION_HANDLING := 0
125
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100126# Flag to enable Branch Target Identification.
127# Internal flag not meant for direct setting.
128# Use BRANCH_PROTECTION to enable BTI.
129ENABLE_BTI := 0
130
131# Flag to enable Pointer Authentication.
132# Internal flag not meant for direct setting.
133# Use BRANCH_PROTECTION to enable PAUTH.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000134ENABLE_PAUTH := 0
135
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000136# Flag to enable AMUv1p1 extension.
137ENABLE_FEAT_AMUv1p1 := 0
138
139# Flag to enable CSV2_2 extension.
140ENABLE_FEAT_CSV2_2 := 0
141
142# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn.
143ENABLE_FEAT_HCX := 0
144
Jayanth Dodderi Chidanand70c9c0b2021-12-15 16:52:10 +0000145# Flag to enable access to the HDFGRTR_EL2 register
146ENABLE_FEAT_FGT := 0
147
148# Flag to enable access to the CNTPOFF_EL2 register
149ENABLE_FEAT_ECV := 0
150
Daniel Boulby928747f2021-05-25 18:09:34 +0100151# Flag to enable use of the DIT feature.
152ENABLE_FEAT_DIT := 0
153
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000154# Flag to enable access to Privileged Access Never bit of PSTATE.
155ENABLE_FEAT_PAN := 0
156
157# Flag to enable access to the Random Number Generator registers
158ENABLE_FEAT_RNG := 0
159
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400160# Flag to enable support for EL3 trapping of reads of the RNDR and RNDRRS
161# registers, by setting SCR_EL3.TRNDR.
162ENABLE_FEAT_RNG_TRAP := 0
163
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000164# Flag to enable Speculation Barrier Instruction
165ENABLE_FEAT_SB := 0
166
167# Flag to enable Secure EL-2 feature.
168ENABLE_FEAT_SEL2 := 0
169
170# Flag to enable Virtualization Host Extensions
171ENABLE_FEAT_VHE := 0
172
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100173# Flag to enable delayed trapping of WFE instruction (FEAT_TWED)
174ENABLE_FEAT_TWED := 0
175
Mark Brownc37eee72023-03-14 20:13:03 +0000176# Flag to enable access to TCR2 (FEAT_TCR2)
177ENABLE_FEAT_TCR2 := 0
178
Mark Brown293a6612023-03-14 20:48:43 +0000179# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE)
180ENABLE_FEAT_S2PIE := 0
181
182# Flag to enable access to Stage 1 Permission Indirection (FEAT_S1PIE)
183ENABLE_FEAT_S1PIE := 0
184
185# Flag to enable access to Stage 2 Permission Overlay (FEAT_S2POE)
186ENABLE_FEAT_S2POE := 0
187
188# Flag to enable access to Stage 1 Permission Overlay (FEAT_S1POE)
189ENABLE_FEAT_S1POE := 0
190
Mark Brown326f2952023-03-14 21:33:04 +0000191# Flag to enable access to Guarded Control Stack (FEAT_GCS)
192ENABLE_FEAT_GCS := 0
193
Sumit Gargeec52442019-11-14 16:33:45 +0530194# By default BL31 encryption disabled
195ENCRYPT_BL31 := 0
196
197# By default BL32 encryption disabled
198ENCRYPT_BL32 := 0
199
200# Default dummy firmware encryption key
201ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef
202
203# Default dummy nonce for firmware encryption
204ENC_NONCE := 1234567890abcdef12345678
205
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100206# Build flag to treat usage of deprecated platform and framework APIs as error.
207ERROR_DEPRECATED := 0
208
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000209# Fault injection support
210FAULT_INJECTION_SUPPORT := 0
211
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000212# Flag to enable architectural features detection mechanism
213FEATURE_DETECTION := 0
214
Masahiro Yamada4d87eb42016-12-25 13:52:22 +0900215# Byte alignment that each component in FIP is aligned to
216FIP_ALIGN := 0
217
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100218# Default FIP file name
219FIP_NAME := fip.bin
220
221# Default FWU_FIP file name
222FWU_FIP_NAME := fwu_fip.bin
223
Sumit Gargeec52442019-11-14 16:33:45 +0530224# By default firmware encryption with SSK
225FW_ENC_STATUS := 0
226
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100227# For Chain of Trust
228GENERATE_COT := 0
229
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100230# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
231# default, they are for Secure EL1.
232GICV2_G0_FOR_EL3 := 0
233
Manish Pandey0e3379d2022-10-10 11:43:08 +0100234# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000235# by lower ELs.
Manish Pandey0e3379d2022-10-10 11:43:08 +0100236HANDLE_EA_EL3_FIRST_NS := 0
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000237
Alexei Fedorovf11aeb72020-10-06 15:54:12 +0100238# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
239# The default value is sha256.
240HASH_ALG := sha256
241
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +0000242# Whether system coherency is managed in hardware, without explicit software
243# operations.
244HW_ASSISTED_COHERENCY := 0
245
Soby Mathew13b16052017-08-31 11:49:32 +0100246# Set the default algorithm for the generation of Trusted Board Boot keys
247KEY_ALG := rsa
248
Leonardo Sandoval849f7af2020-06-18 17:32:55 -0500249# Set the default key size in case KEY_ALG is rsa
250ifeq ($(KEY_ALG),rsa)
251KEY_SIZE := 2048
252endif
253
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000254# Option to build TF with Measured Boot support
255MEASURED_BOOT := 0
256
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100257# NS timer register save and restore
258NS_TIMER_SWITCH := 0
259
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800260# Include lib/libc in the final image
261OVERRIDE_LIBC := 0
262
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100263# Build PL011 UART driver in minimal generic UART mode
264PL011_GENERIC_UART := 0
265
266# By default, consider that the platform's reset address is not programmable.
267# The platform Makefile is free to override this value.
268PROGRAMMABLE_RESET_ADDRESS := 0
269
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000270# Flag used to choose the power state format: Extended State-ID or Original
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100271PSCI_EXTENDED_STATE_ID := 0
272
Wing Li1e9b68a2023-01-26 18:33:36 -0800273# Enable PSCI OS-initiated mode support
274PSCI_OS_INIT_MODE := 0
275
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100276# Enable RAS support
277RAS_EXTENSION := 0
278
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100279# By default, BL1 acts as the reset handler, not BL31
280RESET_TO_BL31 := 0
281
282# For Chain of Trust
283SAVE_KEYS := 0
284
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100285# Software Delegated Exception support
johpow019baade32021-07-08 14:14:00 -0500286SDEI_SUPPORT := 0
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100287
Jayanth Dodderi Chidanand7c7faff2022-10-11 17:16:07 +0100288# True Random Number firmware Interface support
johpow019baade32021-07-08 14:14:00 -0500289TRNG_SUPPORT := 0
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -0500290
Jeremy Linton90cbf522020-11-18 10:12:41 -0600291# SMCCC PCI support
johpow019baade32021-07-08 14:14:00 -0500292SMC_PCI_SUPPORT := 0
Jeremy Linton90cbf522020-11-18 10:12:41 -0600293
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100294# Whether code and read-only data should be put on separate memory pages. The
295# platform Makefile is free to override this value.
296SEPARATE_CODE_AND_RODATA := 0
297
Samuel Holland31a14e12018-10-17 21:40:18 -0500298# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
299# separate memory region, which may be discontiguous from the rest of BL31.
300SEPARATE_NOBITS_REGION := 0
301
Jiafei Pan0824b452022-02-24 10:47:33 +0800302# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory
303# region, platform Makefile is free to override this value.
304SEPARATE_BL2_NOLOAD_REGION := 0
305
Daniel Boulby468f0d72018-09-18 11:45:51 +0100306# If the BL31 image initialisation code is recalimed after use for the secondary
307# cores stack
308RECLAIM_INIT_CODE := 0
309
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100310# SPD choice
311SPD := none
312
Paul Beesleyfe975b42019-09-16 11:29:03 +0000313# Enable the Management Mode (MM)-based Secure Partition Manager implementation
314SPM_MM := 0
Antonio Nino Diaz8cd7ea32018-10-30 11:08:08 +0000315
Marc Bonniciabaac162021-12-01 18:00:40 +0000316# Use the FF-A SPMC implementation in EL3.
317SPMC_AT_EL3 := 0
318
Max Shvetsove7fd80e2020-02-25 13:55:00 +0000319# Use SPM at S-EL2 as a default config for SPMD
320SPMD_SPM_AT_SEL2 := 1
321
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100322# Flag to introduce an infinite loop in BL1 just before it exits into the next
323# image. This is meant to help debugging the post-BL2 phase.
324SPIN_ON_BL1_EXIT := 0
325
326# Flags to build TF with Trusted Boot support
327TRUSTED_BOARD_BOOT := 0
328
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100329# Build option to choose whether Trusted Firmware uses Coherent memory or not.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100330USE_COHERENT_MEM := 1
331
Olivier Deprezcb4c5622019-09-19 17:46:46 +0200332# Build option to add debugfs support
333USE_DEBUGFS := 0
334
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100335# Build option to fconf based io
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100336ARM_IO_IN_DTB := 0
337
338# Build option to support SDEI through fconf
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500339SDEI_IN_FCONF := 0
340
341# Build option to support Secure Interrupt descriptors through fconf
342SEC_INT_DESC_IN_FCONF := 0
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100343
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100344# Build option to choose whether Trusted Firmware uses library at ROM
345USE_ROMLIB := 0
Roberto Vargase92111a2018-05-22 16:05:42 +0100346
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000347# Build option to choose whether the xlat tables of BL images can be read-only.
348# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES,
349# which is the per BL-image option that actually enables the read-only tables
350# API. The reason for having this additional option is to have a common high
351# level makefile where we can check for incompatible features/build options.
352ALLOW_RO_XLAT_TABLES := 0
353
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100354# Chain of trust.
355COT := tbbr
356
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900357# Use tbbr_oid.h instead of platform_oid.h
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100358USE_TBBR_DEFS := 1
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900359
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100360# Build verbosity
361V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100362
363# Whether to enable D-Cache early during warm boot. This is usually
364# applicable for platforms wherein interconnect programming is not
365# required to enable cache coherency after warm reset (eg: single cluster
366# platforms).
367WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armee3457b2017-05-23 09:32:49 +0100368
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100369# Build option to enable/disable the Statistical Profiling Extensions
Andre Przywaraf3e8cfc2022-11-17 16:42:09 +0000370ENABLE_SPE_FOR_NS := 2
dp-armee3457b2017-05-23 09:32:49 +0100371
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100372# SPE is only supported on AArch64 so disable it on AArch32.
dp-armee3457b2017-05-23 09:32:49 +0100373ifeq (${ARCH},aarch32)
Andre Przywara30661a92023-02-03 15:30:14 +0000374 override ENABLE_SPE_FOR_NS := 0
dp-armee3457b2017-05-23 09:32:49 +0100375endif
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100376
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100377# Include Memory Tagging Extension registers in cpu context. This must be set
378# to 1 if the platform wants to use this feature in the Secure world and MTE is
379# enabled at ELX.
johpow01fa59c6f2020-10-02 13:41:11 -0500380CTX_INCLUDE_MTE_REGS := 0
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100381
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000382ENABLE_FEAT_AMU := 0
Chris Kay925fda42021-05-25 10:42:56 +0100383ENABLE_AMU_AUXILIARY_COUNTERS := 0
Chris Kayf11909f2021-08-19 11:21:52 +0100384ENABLE_AMU_FCONF := 0
johpow01fa59c6f2020-10-02 13:41:11 -0500385AMU_RESTRICT_COUNTERS := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100386
johpow019baade32021-07-08 14:14:00 -0500387# Enable SVE for non-secure world by default
Jayanth Dodderi Chidanandd62c6812023-03-07 10:43:19 +0000388ENABLE_SVE_FOR_NS := 2
Yann Gautier7d917672021-11-19 11:35:46 +0100389# SVE is only supported on AArch64 so disable it on AArch32.
390ifeq (${ARCH},aarch32)
391 override ENABLE_SVE_FOR_NS := 0
392endif
johpow019baade32021-07-08 14:14:00 -0500393ENABLE_SVE_FOR_SWD := 0
394
Mark Brown64869972022-04-20 18:14:32 +0100395# Default SVE vector length to maximum architected value
396SVE_VECTOR_LEN := 2048
397
johpow019baade32021-07-08 14:14:00 -0500398# SME defaults to disabled
399ENABLE_SME_FOR_NS := 0
400ENABLE_SME_FOR_SWD := 0
401
402# If SME is enabled then force SVE off
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000403ifneq (${ENABLE_SME_FOR_NS},0)
johpow019baade32021-07-08 14:14:00 -0500404 override ENABLE_SVE_FOR_NS := 0
405 override ENABLE_SVE_FOR_SWD := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100406endif
Justin Chadwell83e04882019-08-20 11:01:52 +0100407
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000408# SME2 defaults to disabled
409ENABLE_SME2_FOR_NS := 0
410
Justin Chadwell83e04882019-08-20 11:01:52 +0100411SANITIZE_UB := off
Soby Mathewad042012019-09-25 14:03:41 +0100412
413# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
414# implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
415# Default: disabled
416USE_SPINLOCK_CAS := 0
zelalem-aweked5f45272019-11-12 16:20:17 -0600417
418# Enable Link Time Optimization
419ENABLE_LTO := 0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000420
Govindraj Raja0264d6c2022-11-21 13:10:40 +0000421# This option will include EL2 registers in cpu context save and restore during
422# EL2 firmware entry/exit. Internal flag not meant for direct setting.
423# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable
424# CTX_INCLUDE_EL2_REGS.
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000425CTX_INCLUDE_EL2_REGS := 0
Manish V Badarkhe75c972a2020-03-22 05:06:38 +0000426
427# Enable Memory tag extension which is supported for architecture greater
428# than Armv8.5-A
429# By default it is set to "no"
430SUPPORT_STACK_MEMTAG := no
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100431
432# Select workaround for AT speculative behaviour.
johpow019baade32021-07-08 14:14:00 -0500433ERRATA_SPECULATIVE_AT := 0
Varun Wadekar92234852020-06-12 10:11:28 -0700434
Manish Pandey7c6fcb42022-09-27 14:30:34 +0100435# Trap RAS error record access from Non secure
436RAS_TRAP_NS_ERR_REC_ACCESS := 0
Manish V Badarkhead339892020-06-29 10:32:53 +0100437
438# Build option to create cot descriptors using fconf
439COT_DESC_IN_DTB := 0
Manish V Badarkhe3589b702020-07-29 10:58:44 +0100440
Juan Pablo Conde3539c742022-10-25 19:41:02 -0400441# Build option to provide OpenSSL directory path
Manish V Badarkhe3589b702020-07-29 10:58:44 +0100442OPENSSL_DIR := /usr
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500443
Salome Thirot0b35da32022-07-14 16:14:15 +0100444# Select the openssl binary provided in OPENSSL_DIR variable
445ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "")
446 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps
447else
448 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin
449endif
450
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500451# Build option to use the SP804 timer instead of the generic one
452USE_SP804_TIMER := 0
Manish V Badarkhe2bb45ff2021-03-16 10:01:27 +0000453
454# Build option to define number of firmware banks, used in firmware update
455# metadata structure.
456NR_OF_FW_BANKS := 2
457
458# Build option to define number of images in firmware bank, used in firmware
459# update metadata structure.
460NR_OF_IMAGES_IN_FW_BANK := 1
Manish V Badarkhe99575e42021-06-25 23:28:59 +0100461
462# Disable Firmware update support by default
463PSA_FWU_SUPPORT := 0
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100464
465# By default, disable access of trace buffer control registers from NS
466# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
467# if FEAT_TRBE is implemented.
468# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in
469# AArch32.
470ifneq (${ARCH},aarch32)
johpow019baade32021-07-08 14:14:00 -0500471 ENABLE_TRBE_FOR_NS := 0
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100472else
johpow019baade32021-07-08 14:14:00 -0500473 override ENABLE_TRBE_FOR_NS := 0
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100474endif
Manish V Badarkhef356f7e2021-06-29 11:44:20 +0100475
johpow0181865962022-01-28 17:06:20 -0600476# By default, disable access to branch record buffer control registers from NS
477# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
478# if FEAT_BRBE is implemented.
479ENABLE_BRBE_FOR_NS := 0
480
Manish V Badarkhef356f7e2021-06-29 11:44:20 +0100481# By default, disable access of trace system registers from NS lower
482# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if
483# system register trace is implemented.
484ENABLE_SYS_REG_TRACE_FOR_NS := 0
Manish V Badarkhe51a97112021-07-08 09:33:18 +0100485
486# By default, disable trace filter control registers access to NS
487# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
488# if FEAT_TRF is implemented.
489ENABLE_TRF_FOR_NS := 0
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +0100490
491# In v8.6+ platforms with delayed trapping of WFE being supported
492# via FEAT_TWED, this flag takes the delay value to be set in the
493# SCR_EL3.TWEDEL(4bit) field, when FEAT_TWED is implemented.
494# By default it takes 0, and need to be updated by the platforms.
495TWED_DELAY := 0
Tamas Banc9ccc272022-01-18 16:20:47 +0100496
497# By default, disable the mocking of RSS provided services
498PLAT_RSS_NOT_SUPPORTED := 0
Manish V Badarkhe191a5fc2022-03-02 12:06:35 +0000499
500# Dynamic Root of Trust for Measurement support
501DRTM_SUPPORT := 0
Okash Khawaja037b56e2022-11-04 12:38:01 +0000502
503# Check platform if cache management operations should be performed.
504# Disabled by default.
505CONDITIONAL_CMO := 0