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Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Alexei Fedorovf11aeb72020-10-06 15:54:12 +01002# Copyright (c) 2016-2020, ARM Limited. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010013# Use T32 by default
14AARCH32_INSTRUCTION_SET := T32
15
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010016# The AArch32 Secure Payload to be built as BL32 image
17AARCH32_SP := none
18
19# The Target build architecture. Supported values are: aarch64, aarch32.
20ARCH := aarch64
21
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000022# ARM Architecture major and minor versions: 8.0 by default.
23ARM_ARCH_MAJOR := 8
24ARM_ARCH_MINOR := 0
25
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010026# Base commit to perform code check on
27BASE_COMMIT := origin/master
28
Roberto Vargase0e99462017-10-30 14:43:43 +000029# Execute BL2 at EL3
30BL2_AT_EL3 := 0
31
Jiafei Pan43a7bf42018-03-21 07:20:09 +000032# BL2 image is stored in XIP memory, for now, this option is only supported
33# when BL2_AT_EL3 is 1.
34BL2_IN_XIP_MEM := 0
35
Hadi Asyrafi461f8f42019-08-20 15:33:27 +080036# Do dcache invalidate upon BL2 entry at EL3
37BL2_INV_DCACHE := 1
38
Alexei Fedorov90f2e882019-05-24 12:17:09 +010039# Select the branch protection features to use.
40BRANCH_PROTECTION := 0
41
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010042# By default, consider that the platform may release several CPUs out of reset.
43# The platform Makefile is free to override this value.
44COLD_BOOT_SINGLE_CPU := 0
45
Julius Wernerb624ae02017-06-09 15:17:15 -070046# Flag to compile in coreboot support code. Exclude by default. The coreboot
47# Makefile system will set this when compiling TF as part of a coreboot image.
48COREBOOT := 0
49
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010050# For Chain of Trust
51CREATE_KEYS := 1
52
53# Build flag to include AArch32 registers in cpu context save and restore during
54# world switch. This flag must be set to 0 for AArch64-only platforms.
55CTX_INCLUDE_AARCH32_REGS := 1
56
57# Include FP registers in cpu context
58CTX_INCLUDE_FPREGS := 0
59
Antonio Nino Diaz594811b2019-01-31 11:58:00 +000060# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
61# must be set to 1 if the platform wants to use this feature in the Secure
62# world. It is not needed to use it in the Non-secure world.
63CTX_INCLUDE_PAUTH_REGS := 0
64
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +010065# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
66# This must be set to 1 if architecture implements Nested Virtualization
67# Extension and platform wants to use this feature in the Secure world
68CTX_INCLUDE_NEVE_REGS := 0
69
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010070# Debug build
71DEBUG := 0
72
Sumit Garg392e4df2019-11-15 10:43:00 +053073# By default disable authenticated decryption support.
74DECRYPTION_SUPPORT := none
75
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010076# Build platform
77DEFAULT_PLAT := fvp
78
Christoph Müllner4f088e42019-04-24 09:45:30 +020079# Disable the generation of the binary image (ELF only).
80DISABLE_BIN_GENERATION := 0
81
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +000082# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards
83# compatibility.
84DISABLE_MTPMU := 0
85
Soby Mathew9fe88042018-03-26 12:43:37 +010086# Enable capability to disable authentication dynamically. Only meant for
87# development platforms.
88DYN_DISABLE_AUTH := 0
89
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +010090# Build option to enable MPAM for lower ELs
91ENABLE_MPAM_FOR_LOWER_ELS := 0
92
Soby Mathew078f1a42018-08-28 11:13:55 +010093# Flag to Enable Position Independant support (PIE)
94ENABLE_PIE := 0
95
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010096# Flag to enable Performance Measurement Framework
97ENABLE_PMF := 0
98
99# Flag to enable PSCI STATs functionality
100ENABLE_PSCI_STAT := 0
101
102# Flag to enable runtime instrumentation using PMF
103ENABLE_RUNTIME_INSTRUMENTATION := 0
104
Douglas Raillard306593d2017-02-24 18:14:15 +0000105# Flag to enable stack corruption protection
106ENABLE_STACK_PROTECTOR := 0
107
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100108# Flag to enable exception handling in EL3
109EL3_EXCEPTION_HANDLING := 0
110
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100111# Flag to enable Branch Target Identification.
112# Internal flag not meant for direct setting.
113# Use BRANCH_PROTECTION to enable BTI.
114ENABLE_BTI := 0
115
116# Flag to enable Pointer Authentication.
117# Internal flag not meant for direct setting.
118# Use BRANCH_PROTECTION to enable PAUTH.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000119ENABLE_PAUTH := 0
120
Sumit Gargeec52442019-11-14 16:33:45 +0530121# By default BL31 encryption disabled
122ENCRYPT_BL31 := 0
123
124# By default BL32 encryption disabled
125ENCRYPT_BL32 := 0
126
127# Default dummy firmware encryption key
128ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef
129
130# Default dummy nonce for firmware encryption
131ENC_NONCE := 1234567890abcdef12345678
132
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100133# Build flag to treat usage of deprecated platform and framework APIs as error.
134ERROR_DEPRECATED := 0
135
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000136# Fault injection support
137FAULT_INJECTION_SUPPORT := 0
138
Masahiro Yamada4d87eb42016-12-25 13:52:22 +0900139# Byte alignment that each component in FIP is aligned to
140FIP_ALIGN := 0
141
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100142# Default FIP file name
143FIP_NAME := fip.bin
144
145# Default FWU_FIP file name
146FWU_FIP_NAME := fwu_fip.bin
147
Sumit Gargeec52442019-11-14 16:33:45 +0530148# By default firmware encryption with SSK
149FW_ENC_STATUS := 0
150
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100151# For Chain of Trust
152GENERATE_COT := 0
153
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100154# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
155# default, they are for Secure EL1.
156GICV2_G0_FOR_EL3 := 0
157
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000158# Route External Aborts to EL3. Disabled by default; External Aborts are handled
159# by lower ELs.
160HANDLE_EA_EL3_FIRST := 0
161
Alexei Fedorovf11aeb72020-10-06 15:54:12 +0100162# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
163# The default value is sha256.
164HASH_ALG := sha256
165
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +0000166# Whether system coherency is managed in hardware, without explicit software
167# operations.
168HW_ASSISTED_COHERENCY := 0
169
Soby Mathew13b16052017-08-31 11:49:32 +0100170# Set the default algorithm for the generation of Trusted Board Boot keys
171KEY_ALG := rsa
172
Leonardo Sandoval849f7af2020-06-18 17:32:55 -0500173# Set the default key size in case KEY_ALG is rsa
174ifeq ($(KEY_ALG),rsa)
175KEY_SIZE := 2048
176endif
177
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000178# Option to build TF with Measured Boot support
179MEASURED_BOOT := 0
180
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100181# NS timer register save and restore
182NS_TIMER_SWITCH := 0
183
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800184# Include lib/libc in the final image
185OVERRIDE_LIBC := 0
186
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100187# Build PL011 UART driver in minimal generic UART mode
188PL011_GENERIC_UART := 0
189
190# By default, consider that the platform's reset address is not programmable.
191# The platform Makefile is free to override this value.
192PROGRAMMABLE_RESET_ADDRESS := 0
193
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000194# Flag used to choose the power state format: Extended State-ID or Original
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100195PSCI_EXTENDED_STATE_ID := 0
196
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100197# Enable RAS support
198RAS_EXTENSION := 0
199
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100200# By default, BL1 acts as the reset handler, not BL31
201RESET_TO_BL31 := 0
202
203# For Chain of Trust
204SAVE_KEYS := 0
205
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100206# Software Delegated Exception support
207SDEI_SUPPORT := 0
208
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100209# Whether code and read-only data should be put on separate memory pages. The
210# platform Makefile is free to override this value.
211SEPARATE_CODE_AND_RODATA := 0
212
Samuel Holland31a14e12018-10-17 21:40:18 -0500213# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
214# separate memory region, which may be discontiguous from the rest of BL31.
215SEPARATE_NOBITS_REGION := 0
216
Daniel Boulby468f0d72018-09-18 11:45:51 +0100217# If the BL31 image initialisation code is recalimed after use for the secondary
218# cores stack
219RECLAIM_INIT_CODE := 0
220
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100221# SPD choice
222SPD := none
223
Paul Beesleyfe975b42019-09-16 11:29:03 +0000224# Enable the Management Mode (MM)-based Secure Partition Manager implementation
225SPM_MM := 0
Antonio Nino Diaz8cd7ea32018-10-30 11:08:08 +0000226
Max Shvetsove7fd80e2020-02-25 13:55:00 +0000227# Use SPM at S-EL2 as a default config for SPMD
228SPMD_SPM_AT_SEL2 := 1
229
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100230# Flag to introduce an infinite loop in BL1 just before it exits into the next
231# image. This is meant to help debugging the post-BL2 phase.
232SPIN_ON_BL1_EXIT := 0
233
234# Flags to build TF with Trusted Boot support
235TRUSTED_BOARD_BOOT := 0
236
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100237# Build option to choose whether Trusted Firmware uses Coherent memory or not.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100238USE_COHERENT_MEM := 1
239
Olivier Deprezcb4c5622019-09-19 17:46:46 +0200240# Build option to add debugfs support
241USE_DEBUGFS := 0
242
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100243# Build option to fconf based io
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100244ARM_IO_IN_DTB := 0
245
246# Build option to support SDEI through fconf
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500247SDEI_IN_FCONF := 0
248
249# Build option to support Secure Interrupt descriptors through fconf
250SEC_INT_DESC_IN_FCONF := 0
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100251
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100252# Build option to choose whether Trusted Firmware uses library at ROM
253USE_ROMLIB := 0
Roberto Vargase92111a2018-05-22 16:05:42 +0100254
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000255# Build option to choose whether the xlat tables of BL images can be read-only.
256# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES,
257# which is the per BL-image option that actually enables the read-only tables
258# API. The reason for having this additional option is to have a common high
259# level makefile where we can check for incompatible features/build options.
260ALLOW_RO_XLAT_TABLES := 0
261
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100262# Chain of trust.
263COT := tbbr
264
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900265# Use tbbr_oid.h instead of platform_oid.h
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100266USE_TBBR_DEFS := 1
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900267
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100268# Build verbosity
269V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100270
271# Whether to enable D-Cache early during warm boot. This is usually
272# applicable for platforms wherein interconnect programming is not
273# required to enable cache coherency after warm reset (eg: single cluster
274# platforms).
275WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armee3457b2017-05-23 09:32:49 +0100276
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100277# Build option to enable/disable the Statistical Profiling Extensions
dp-armee3457b2017-05-23 09:32:49 +0100278ENABLE_SPE_FOR_LOWER_ELS := 1
279
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100280# SPE is only supported on AArch64 so disable it on AArch32.
dp-armee3457b2017-05-23 09:32:49 +0100281ifeq (${ARCH},aarch32)
282 override ENABLE_SPE_FOR_LOWER_ELS := 0
dp-armee3457b2017-05-23 09:32:49 +0100283endif
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100284
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100285# Include Memory Tagging Extension registers in cpu context. This must be set
286# to 1 if the platform wants to use this feature in the Secure world and MTE is
287# enabled at ELX.
288CTX_INCLUDE_MTE_REGS := 0
289
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100290ENABLE_AMU := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100291
292# By default, enable Scalable Vector Extension if implemented for Non-secure
293# lower ELs
294# Note SVE is only supported on AArch64 - therefore do not enable in AArch32
295ifneq (${ARCH},aarch32)
296 ENABLE_SVE_FOR_NS := 1
297else
298 override ENABLE_SVE_FOR_NS := 0
299endif
Justin Chadwell83e04882019-08-20 11:01:52 +0100300
301SANITIZE_UB := off
Soby Mathewad042012019-09-25 14:03:41 +0100302
303# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
304# implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
305# Default: disabled
306USE_SPINLOCK_CAS := 0
zelalem-aweked5f45272019-11-12 16:20:17 -0600307
308# Enable Link Time Optimization
309ENABLE_LTO := 0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000310
311# Build flag to include EL2 registers in cpu context save and restore during
312# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option.
313# Default is 0.
314CTX_INCLUDE_EL2_REGS := 0
Manish V Badarkhe75c972a2020-03-22 05:06:38 +0000315
316# Enable Memory tag extension which is supported for architecture greater
317# than Armv8.5-A
318# By default it is set to "no"
319SUPPORT_STACK_MEMTAG := no
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100320
321# Select workaround for AT speculative behaviour.
322ERRATA_SPECULATIVE_AT := 0
Varun Wadekar92234852020-06-12 10:11:28 -0700323
324# Trap RAS error record access from lower EL
325RAS_TRAP_LOWER_EL_ERR_ACCESS := 0
Manish V Badarkhead339892020-06-29 10:32:53 +0100326
327# Build option to create cot descriptors using fconf
328COT_DESC_IN_DTB := 0
Manish V Badarkhe3589b702020-07-29 10:58:44 +0100329
330# Build option to provide openssl directory path
331OPENSSL_DIR := /usr
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500332
333# Build option to use the SP804 timer instead of the generic one
334USE_SP804_TIMER := 0