blob: 551b6897735cdbc18358cf3d7f0ba23a93fd48a4 [file] [log] [blame]
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01001#
Zelalem Aweke4d37db82021-07-11 18:33:20 -05002# Copyright (c) 2016-2021, Arm Limited. All rights reserved.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharan615ff392016-10-24 14:31:51 +01005#
6
7# Default, static values for build variables, listed in alphabetic order.
8# Dependencies between build options, if any, are handled in the top-level
9# Makefile, after this file is included. This ensures that the former is better
10# poised to handle dependencies, as all build variables would have a default
11# value by then.
12
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010013# Use T32 by default
14AARCH32_INSTRUCTION_SET := T32
15
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010016# The AArch32 Secure Payload to be built as BL32 image
17AARCH32_SP := none
18
19# The Target build architecture. Supported values are: aarch64, aarch32.
20ARCH := aarch64
21
Alexei Fedorov132e6652020-12-07 16:38:53 +000022# ARM Architecture feature modifiers: none by default
23ARM_ARCH_FEATURE := none
24
Jeenu Viswambharanfca76802017-01-16 16:52:35 +000025# ARM Architecture major and minor versions: 8.0 by default.
26ARM_ARCH_MAJOR := 8
27ARM_ARCH_MINOR := 0
28
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010029# Base commit to perform code check on
30BASE_COMMIT := origin/master
31
Roberto Vargase0e99462017-10-30 14:43:43 +000032# Execute BL2 at EL3
33BL2_AT_EL3 := 0
34
Balint Dobszay719ba9c2021-03-26 16:23:18 +010035# Only use SP packages if SP layout JSON is defined
36BL2_ENABLE_SP_LOAD := 0
37
Jiafei Pan43a7bf42018-03-21 07:20:09 +000038# BL2 image is stored in XIP memory, for now, this option is only supported
39# when BL2_AT_EL3 is 1.
40BL2_IN_XIP_MEM := 0
41
Hadi Asyrafi461f8f42019-08-20 15:33:27 +080042# Do dcache invalidate upon BL2 entry at EL3
43BL2_INV_DCACHE := 1
44
Alexei Fedorov90f2e882019-05-24 12:17:09 +010045# Select the branch protection features to use.
46BRANCH_PROTECTION := 0
47
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010048# By default, consider that the platform may release several CPUs out of reset.
49# The platform Makefile is free to override this value.
50COLD_BOOT_SINGLE_CPU := 0
51
Julius Wernerb624ae02017-06-09 15:17:15 -070052# Flag to compile in coreboot support code. Exclude by default. The coreboot
53# Makefile system will set this when compiling TF as part of a coreboot image.
54COREBOOT := 0
55
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010056# For Chain of Trust
57CREATE_KEYS := 1
58
59# Build flag to include AArch32 registers in cpu context save and restore during
60# world switch. This flag must be set to 0 for AArch64-only platforms.
61CTX_INCLUDE_AARCH32_REGS := 1
62
63# Include FP registers in cpu context
64CTX_INCLUDE_FPREGS := 0
65
Antonio Nino Diaz594811b2019-01-31 11:58:00 +000066# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
67# must be set to 1 if the platform wants to use this feature in the Secure
68# world. It is not needed to use it in the Non-secure world.
69CTX_INCLUDE_PAUTH_REGS := 0
70
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +010071# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
72# This must be set to 1 if architecture implements Nested Virtualization
73# Extension and platform wants to use this feature in the Secure world
74CTX_INCLUDE_NEVE_REGS := 0
75
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010076# Debug build
77DEBUG := 0
78
Sumit Garg392e4df2019-11-15 10:43:00 +053079# By default disable authenticated decryption support.
80DECRYPTION_SUPPORT := none
81
Jeenu Viswambharan615ff392016-10-24 14:31:51 +010082# Build platform
83DEFAULT_PLAT := fvp
84
Christoph Müllner4f088e42019-04-24 09:45:30 +020085# Disable the generation of the binary image (ELF only).
86DISABLE_BIN_GENERATION := 0
87
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +000088# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards
89# compatibility.
90DISABLE_MTPMU := 0
91
Soby Mathew9fe88042018-03-26 12:43:37 +010092# Enable capability to disable authentication dynamically. Only meant for
93# development platforms.
94DYN_DISABLE_AUTH := 0
95
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +010096# Build option to enable MPAM for lower ELs
97ENABLE_MPAM_FOR_LOWER_ELS := 0
98
Chris Kay03be39d2021-05-05 13:38:30 +010099# Enable the Maximum Power Mitigation Mechanism on supporting cores.
100ENABLE_MPMM := 0
101
102# Enable MPMM configuration via FCONF.
103ENABLE_MPMM_FCONF := 0
104
Soby Mathew078f1a42018-08-28 11:13:55 +0100105# Flag to Enable Position Independant support (PIE)
106ENABLE_PIE := 0
107
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100108# Flag to enable Performance Measurement Framework
109ENABLE_PMF := 0
110
111# Flag to enable PSCI STATs functionality
112ENABLE_PSCI_STAT := 0
113
Zelalem Aweke4d37db82021-07-11 18:33:20 -0500114# Flag to enable Realm Management Extension (FEAT_RME)
115ENABLE_RME := 0
116
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100117# Flag to enable runtime instrumentation using PMF
118ENABLE_RUNTIME_INSTRUMENTATION := 0
119
Douglas Raillard306593d2017-02-24 18:14:15 +0000120# Flag to enable stack corruption protection
121ENABLE_STACK_PROTECTOR := 0
122
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100123# Flag to enable exception handling in EL3
124EL3_EXCEPTION_HANDLING := 0
125
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100126# Flag to enable Branch Target Identification.
127# Internal flag not meant for direct setting.
128# Use BRANCH_PROTECTION to enable BTI.
129ENABLE_BTI := 0
130
131# Flag to enable Pointer Authentication.
132# Internal flag not meant for direct setting.
133# Use BRANCH_PROTECTION to enable PAUTH.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000134ENABLE_PAUTH := 0
135
johpow01f91e59f2021-08-04 19:38:18 -0500136# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn.
johpow019baade32021-07-08 14:14:00 -0500137ENABLE_FEAT_HCX := 0
johpow01f91e59f2021-08-04 19:38:18 -0500138
Jayanth Dodderi Chidanand13ae0f42021-11-25 14:59:30 +0000139# Flag to enable access to the HAFGRTR_EL2 register
140ENABLE_FEAT_AMUv1 := 0
141
Jayanth Dodderi Chidanand70c9c0b2021-12-15 16:52:10 +0000142# Flag to enable access to the HDFGRTR_EL2 register
143ENABLE_FEAT_FGT := 0
144
145# Flag to enable access to the CNTPOFF_EL2 register
146ENABLE_FEAT_ECV := 0
147
Sumit Gargeec52442019-11-14 16:33:45 +0530148# By default BL31 encryption disabled
149ENCRYPT_BL31 := 0
150
151# By default BL32 encryption disabled
152ENCRYPT_BL32 := 0
153
154# Default dummy firmware encryption key
155ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef
156
157# Default dummy nonce for firmware encryption
158ENC_NONCE := 1234567890abcdef12345678
159
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100160# Build flag to treat usage of deprecated platform and framework APIs as error.
161ERROR_DEPRECATED := 0
162
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000163# Fault injection support
164FAULT_INJECTION_SUPPORT := 0
165
Masahiro Yamada4d87eb42016-12-25 13:52:22 +0900166# Byte alignment that each component in FIP is aligned to
167FIP_ALIGN := 0
168
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100169# Default FIP file name
170FIP_NAME := fip.bin
171
172# Default FWU_FIP file name
173FWU_FIP_NAME := fwu_fip.bin
174
Sumit Gargeec52442019-11-14 16:33:45 +0530175# By default firmware encryption with SSK
176FW_ENC_STATUS := 0
177
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100178# For Chain of Trust
179GENERATE_COT := 0
180
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100181# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
182# default, they are for Secure EL1.
183GICV2_G0_FOR_EL3 := 0
184
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000185# Route External Aborts to EL3. Disabled by default; External Aborts are handled
186# by lower ELs.
187HANDLE_EA_EL3_FIRST := 0
188
Alexei Fedorovf11aeb72020-10-06 15:54:12 +0100189# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
190# The default value is sha256.
191HASH_ALG := sha256
192
Jeenu Viswambharana10d64e2017-01-04 13:51:42 +0000193# Whether system coherency is managed in hardware, without explicit software
194# operations.
195HW_ASSISTED_COHERENCY := 0
196
Soby Mathew13b16052017-08-31 11:49:32 +0100197# Set the default algorithm for the generation of Trusted Board Boot keys
198KEY_ALG := rsa
199
Leonardo Sandoval849f7af2020-06-18 17:32:55 -0500200# Set the default key size in case KEY_ALG is rsa
201ifeq ($(KEY_ALG),rsa)
202KEY_SIZE := 2048
203endif
204
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000205# Option to build TF with Measured Boot support
206MEASURED_BOOT := 0
207
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100208# NS timer register save and restore
209NS_TIMER_SWITCH := 0
210
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800211# Include lib/libc in the final image
212OVERRIDE_LIBC := 0
213
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100214# Build PL011 UART driver in minimal generic UART mode
215PL011_GENERIC_UART := 0
216
217# By default, consider that the platform's reset address is not programmable.
218# The platform Makefile is free to override this value.
219PROGRAMMABLE_RESET_ADDRESS := 0
220
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000221# Flag used to choose the power state format: Extended State-ID or Original
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100222PSCI_EXTENDED_STATE_ID := 0
223
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100224# Enable RAS support
225RAS_EXTENSION := 0
226
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100227# By default, BL1 acts as the reset handler, not BL31
228RESET_TO_BL31 := 0
229
230# For Chain of Trust
231SAVE_KEYS := 0
232
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100233# Software Delegated Exception support
johpow019baade32021-07-08 14:14:00 -0500234SDEI_SUPPORT := 0
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100235
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -0500236# True Random Number firmware Interface
johpow019baade32021-07-08 14:14:00 -0500237TRNG_SUPPORT := 0
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -0500238
Jeremy Linton90cbf522020-11-18 10:12:41 -0600239# SMCCC PCI support
johpow019baade32021-07-08 14:14:00 -0500240SMC_PCI_SUPPORT := 0
Jeremy Linton90cbf522020-11-18 10:12:41 -0600241
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100242# Whether code and read-only data should be put on separate memory pages. The
243# platform Makefile is free to override this value.
244SEPARATE_CODE_AND_RODATA := 0
245
Samuel Holland31a14e12018-10-17 21:40:18 -0500246# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
247# separate memory region, which may be discontiguous from the rest of BL31.
248SEPARATE_NOBITS_REGION := 0
249
Daniel Boulby468f0d72018-09-18 11:45:51 +0100250# If the BL31 image initialisation code is recalimed after use for the secondary
251# cores stack
252RECLAIM_INIT_CODE := 0
253
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100254# SPD choice
255SPD := none
256
Paul Beesleyfe975b42019-09-16 11:29:03 +0000257# Enable the Management Mode (MM)-based Secure Partition Manager implementation
258SPM_MM := 0
Antonio Nino Diaz8cd7ea32018-10-30 11:08:08 +0000259
Max Shvetsove7fd80e2020-02-25 13:55:00 +0000260# Use SPM at S-EL2 as a default config for SPMD
261SPMD_SPM_AT_SEL2 := 1
262
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100263# Flag to introduce an infinite loop in BL1 just before it exits into the next
264# image. This is meant to help debugging the post-BL2 phase.
265SPIN_ON_BL1_EXIT := 0
266
267# Flags to build TF with Trusted Boot support
268TRUSTED_BOARD_BOOT := 0
269
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100270# Build option to choose whether Trusted Firmware uses Coherent memory or not.
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100271USE_COHERENT_MEM := 1
272
Olivier Deprezcb4c5622019-09-19 17:46:46 +0200273# Build option to add debugfs support
274USE_DEBUGFS := 0
275
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100276# Build option to fconf based io
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100277ARM_IO_IN_DTB := 0
278
279# Build option to support SDEI through fconf
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500280SDEI_IN_FCONF := 0
281
282# Build option to support Secure Interrupt descriptors through fconf
283SEC_INT_DESC_IN_FCONF := 0
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100284
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100285# Build option to choose whether Trusted Firmware uses library at ROM
286USE_ROMLIB := 0
Roberto Vargase92111a2018-05-22 16:05:42 +0100287
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000288# Build option to choose whether the xlat tables of BL images can be read-only.
289# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES,
290# which is the per BL-image option that actually enables the read-only tables
291# API. The reason for having this additional option is to have a common high
292# level makefile where we can check for incompatible features/build options.
293ALLOW_RO_XLAT_TABLES := 0
294
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100295# Chain of trust.
296COT := tbbr
297
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900298# Use tbbr_oid.h instead of platform_oid.h
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +0100299USE_TBBR_DEFS := 1
Masahiro Yamadaa27c1662017-05-22 12:11:24 +0900300
Jeenu Viswambharan615ff392016-10-24 14:31:51 +0100301# Build verbosity
302V := 0
Soby Mathew043fe9c2017-04-10 22:35:42 +0100303
304# Whether to enable D-Cache early during warm boot. This is usually
305# applicable for platforms wherein interconnect programming is not
306# required to enable cache coherency after warm reset (eg: single cluster
307# platforms).
308WARMBOOT_ENABLE_DCACHE_EARLY := 0
dp-armee3457b2017-05-23 09:32:49 +0100309
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100310# Build option to enable/disable the Statistical Profiling Extensions
dp-armee3457b2017-05-23 09:32:49 +0100311ENABLE_SPE_FOR_LOWER_ELS := 1
312
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100313# SPE is only supported on AArch64 so disable it on AArch32.
dp-armee3457b2017-05-23 09:32:49 +0100314ifeq (${ARCH},aarch32)
johpow019baade32021-07-08 14:14:00 -0500315 override ENABLE_SPE_FOR_LOWER_ELS := 0
dp-armee3457b2017-05-23 09:32:49 +0100316endif
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100317
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100318# Include Memory Tagging Extension registers in cpu context. This must be set
319# to 1 if the platform wants to use this feature in the Secure world and MTE is
320# enabled at ELX.
johpow01fa59c6f2020-10-02 13:41:11 -0500321CTX_INCLUDE_MTE_REGS := 0
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100322
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100323ENABLE_AMU := 0
Chris Kay925fda42021-05-25 10:42:56 +0100324ENABLE_AMU_AUXILIARY_COUNTERS := 0
Chris Kayf11909f2021-08-19 11:21:52 +0100325ENABLE_AMU_FCONF := 0
johpow01fa59c6f2020-10-02 13:41:11 -0500326AMU_RESTRICT_COUNTERS := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100327
johpow019baade32021-07-08 14:14:00 -0500328# Enable SVE for non-secure world by default
329ENABLE_SVE_FOR_NS := 1
Yann Gautier7d917672021-11-19 11:35:46 +0100330# SVE is only supported on AArch64 so disable it on AArch32.
331ifeq (${ARCH},aarch32)
332 override ENABLE_SVE_FOR_NS := 0
333endif
johpow019baade32021-07-08 14:14:00 -0500334ENABLE_SVE_FOR_SWD := 0
335
336# SME defaults to disabled
337ENABLE_SME_FOR_NS := 0
338ENABLE_SME_FOR_SWD := 0
339
340# If SME is enabled then force SVE off
341ifeq (${ENABLE_SME_FOR_NS},1)
342 override ENABLE_SVE_FOR_NS := 0
343 override ENABLE_SVE_FOR_SWD := 0
David Cunadoce88eee2017-10-20 11:30:57 +0100344endif
Justin Chadwell83e04882019-08-20 11:01:52 +0100345
346SANITIZE_UB := off
Soby Mathewad042012019-09-25 14:03:41 +0100347
348# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
349# implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
350# Default: disabled
351USE_SPINLOCK_CAS := 0
zelalem-aweked5f45272019-11-12 16:20:17 -0600352
353# Enable Link Time Optimization
354ENABLE_LTO := 0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000355
356# Build flag to include EL2 registers in cpu context save and restore during
357# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option.
358# Default is 0.
359CTX_INCLUDE_EL2_REGS := 0
Manish V Badarkhe75c972a2020-03-22 05:06:38 +0000360
361# Enable Memory tag extension which is supported for architecture greater
362# than Armv8.5-A
363# By default it is set to "no"
364SUPPORT_STACK_MEMTAG := no
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100365
366# Select workaround for AT speculative behaviour.
johpow019baade32021-07-08 14:14:00 -0500367ERRATA_SPECULATIVE_AT := 0
Varun Wadekar92234852020-06-12 10:11:28 -0700368
369# Trap RAS error record access from lower EL
370RAS_TRAP_LOWER_EL_ERR_ACCESS := 0
Manish V Badarkhead339892020-06-29 10:32:53 +0100371
372# Build option to create cot descriptors using fconf
373COT_DESC_IN_DTB := 0
Manish V Badarkhe3589b702020-07-29 10:58:44 +0100374
375# Build option to provide openssl directory path
376OPENSSL_DIR := /usr
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500377
378# Build option to use the SP804 timer instead of the generic one
379USE_SP804_TIMER := 0
Manish V Badarkhe2bb45ff2021-03-16 10:01:27 +0000380
381# Build option to define number of firmware banks, used in firmware update
382# metadata structure.
383NR_OF_FW_BANKS := 2
384
385# Build option to define number of images in firmware bank, used in firmware
386# update metadata structure.
387NR_OF_IMAGES_IN_FW_BANK := 1
Manish V Badarkhe99575e42021-06-25 23:28:59 +0100388
389# Disable Firmware update support by default
390PSA_FWU_SUPPORT := 0
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100391
392# By default, disable access of trace buffer control registers from NS
393# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
394# if FEAT_TRBE is implemented.
395# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in
396# AArch32.
397ifneq (${ARCH},aarch32)
johpow019baade32021-07-08 14:14:00 -0500398 ENABLE_TRBE_FOR_NS := 0
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100399else
johpow019baade32021-07-08 14:14:00 -0500400 override ENABLE_TRBE_FOR_NS := 0
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100401endif
Manish V Badarkhef356f7e2021-06-29 11:44:20 +0100402
403# By default, disable access of trace system registers from NS lower
404# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if
405# system register trace is implemented.
406ENABLE_SYS_REG_TRACE_FOR_NS := 0
Manish V Badarkhe51a97112021-07-08 09:33:18 +0100407
408# By default, disable trace filter control registers access to NS
409# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
410# if FEAT_TRF is implemented.
411ENABLE_TRF_FOR_NS := 0