Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | #include <arch.h> |
| 31 | #include <arch_helpers.h> |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 32 | #include <assert.h> |
Yatharth Kochar | 3c0087a | 2016-04-14 14:49:37 +0100 | [diff] [blame] | 33 | #include <debug.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 34 | #include <mmio.h> |
| 35 | #include <plat_arm.h> |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 36 | #include <platform_def.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 37 | #include <xlat_tables.h> |
| 38 | |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 39 | extern const mmap_region_t plat_arm_mmap[]; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 40 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 41 | /* Weak definitions may be overridden in specific ARM standard platform */ |
| 42 | #pragma weak plat_get_ns_image_entrypoint |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 43 | #pragma weak plat_arm_get_mmap |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 44 | |
| 45 | /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid |
| 46 | * conflicts with the definition in plat/common. */ |
| 47 | #if ERROR_DEPRECATED |
| 48 | #pragma weak plat_get_syscnt_freq2 |
| 49 | #else |
Yatharth Kochar | 3c0087a | 2016-04-14 14:49:37 +0100 | [diff] [blame] | 50 | #pragma weak plat_get_syscnt_freq |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 51 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 52 | |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 53 | /* |
| 54 | * Set up the page tables for the generic and platform-specific memory regions. |
| 55 | * The extents of the generic memory regions are specified by the function |
| 56 | * arguments and consist of: |
| 57 | * - Trusted SRAM seen by the BL image; |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 58 | * - Code section; |
| 59 | * - Read-only data section; |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 60 | * - Coherent memory region, if applicable. |
| 61 | */ |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 62 | void arm_setup_page_tables(uintptr_t total_base, |
| 63 | size_t total_size, |
| 64 | uintptr_t code_start, |
| 65 | uintptr_t code_limit, |
| 66 | uintptr_t rodata_start, |
| 67 | uintptr_t rodata_limit |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 68 | #if USE_COHERENT_MEM |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 69 | , |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 70 | uintptr_t coh_start, |
| 71 | uintptr_t coh_limit |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 72 | #endif |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 73 | ) |
| 74 | { |
| 75 | /* |
| 76 | * Map the Trusted SRAM with appropriate memory attributes. |
| 77 | * Subsequent mappings will adjust the attributes for specific regions. |
| 78 | */ |
Sandrine Bailleux | 12997c5 | 2016-06-20 13:57:10 +0100 | [diff] [blame] | 79 | VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", |
| 80 | (void *) total_base, (void *) (total_base + total_size)); |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 81 | mmap_add_region(total_base, total_base, |
| 82 | total_size, |
| 83 | MT_MEMORY | MT_RW | MT_SECURE); |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 84 | |
| 85 | /* Re-map the code section */ |
Sandrine Bailleux | 12997c5 | 2016-06-20 13:57:10 +0100 | [diff] [blame] | 86 | VERBOSE("Code region: %p - %p\n", |
| 87 | (void *) code_start, (void *) code_limit); |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 88 | mmap_add_region(code_start, code_start, |
| 89 | code_limit - code_start, |
| 90 | MT_CODE | MT_SECURE); |
| 91 | |
| 92 | /* Re-map the read-only data section */ |
Sandrine Bailleux | 12997c5 | 2016-06-20 13:57:10 +0100 | [diff] [blame] | 93 | VERBOSE("Read-only data region: %p - %p\n", |
| 94 | (void *) rodata_start, (void *) rodata_limit); |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 95 | mmap_add_region(rodata_start, rodata_start, |
| 96 | rodata_limit - rodata_start, |
| 97 | MT_RO_DATA | MT_SECURE); |
| 98 | |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 99 | #if USE_COHERENT_MEM |
| 100 | /* Re-map the coherent memory region */ |
Sandrine Bailleux | 12997c5 | 2016-06-20 13:57:10 +0100 | [diff] [blame] | 101 | VERBOSE("Coherent region: %p - %p\n", |
| 102 | (void *) coh_start, (void *) coh_limit); |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 103 | mmap_add_region(coh_start, coh_start, |
| 104 | coh_limit - coh_start, |
| 105 | MT_DEVICE | MT_RW | MT_SECURE); |
| 106 | #endif |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame] | 107 | |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 108 | /* Now (re-)map the platform-specific memory regions */ |
| 109 | mmap_add(plat_arm_get_mmap()); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 110 | |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 111 | /* Create the page tables to reflect the above mappings */ |
| 112 | init_xlat_tables(); |
| 113 | } |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 114 | |
Soby Mathew | 21f9361 | 2016-03-23 10:11:10 +0000 | [diff] [blame] | 115 | uintptr_t plat_get_ns_image_entrypoint(void) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 116 | { |
| 117 | return PLAT_ARM_NS_IMAGE_OFFSET; |
| 118 | } |
| 119 | |
| 120 | /******************************************************************************* |
| 121 | * Gets SPSR for BL32 entry |
| 122 | ******************************************************************************/ |
| 123 | uint32_t arm_get_spsr_for_bl32_entry(void) |
| 124 | { |
| 125 | /* |
| 126 | * The Secure Payload Dispatcher service is responsible for |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 127 | * setting the SPSR prior to entry into the BL32 image. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 128 | */ |
| 129 | return 0; |
| 130 | } |
| 131 | |
| 132 | /******************************************************************************* |
| 133 | * Gets SPSR for BL33 entry |
| 134 | ******************************************************************************/ |
| 135 | uint32_t arm_get_spsr_for_bl33_entry(void) |
| 136 | { |
| 137 | unsigned long el_status; |
| 138 | unsigned int mode; |
| 139 | uint32_t spsr; |
| 140 | |
| 141 | /* Figure out what mode we enter the non-secure world in */ |
| 142 | el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; |
| 143 | el_status &= ID_AA64PFR0_ELX_MASK; |
| 144 | |
| 145 | mode = (el_status) ? MODE_EL2 : MODE_EL1; |
| 146 | |
| 147 | /* |
| 148 | * TODO: Consider the possibility of specifying the SPSR in |
| 149 | * the FIP ToC and allowing the platform to have a say as |
| 150 | * well. |
| 151 | */ |
| 152 | spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
| 153 | return spsr; |
| 154 | } |
| 155 | |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 156 | /******************************************************************************* |
| 157 | * Configures access to the system counter timer module. |
| 158 | ******************************************************************************/ |
Soren Brinkmann | 3d80b71 | 2016-03-06 20:23:39 -0800 | [diff] [blame] | 159 | #ifdef ARM_SYS_TIMCTL_BASE |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 160 | void arm_configure_sys_timer(void) |
| 161 | { |
| 162 | unsigned int reg_val; |
| 163 | |
Juan Castillo | aadf19a | 2015-11-06 16:02:32 +0000 | [diff] [blame] | 164 | #if ARM_CONFIG_CNTACR |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 165 | reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); |
| 166 | reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); |
| 167 | reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); |
| 168 | mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); |
Juan Castillo | aadf19a | 2015-11-06 16:02:32 +0000 | [diff] [blame] | 169 | #endif /* ARM_CONFIG_CNTACR */ |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 170 | |
| 171 | reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); |
| 172 | mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); |
| 173 | } |
Soren Brinkmann | 3d80b71 | 2016-03-06 20:23:39 -0800 | [diff] [blame] | 174 | #endif /* ARM_SYS_TIMCTL_BASE */ |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 175 | |
| 176 | /******************************************************************************* |
| 177 | * Returns ARM platform specific memory map regions. |
| 178 | ******************************************************************************/ |
| 179 | const mmap_region_t *plat_arm_get_mmap(void) |
| 180 | { |
| 181 | return plat_arm_mmap; |
| 182 | } |
Yatharth Kochar | 3c0087a | 2016-04-14 14:49:37 +0100 | [diff] [blame] | 183 | |
Yatharth Kochar | 0b49fb7 | 2016-04-26 10:36:29 +0100 | [diff] [blame] | 184 | #ifdef ARM_SYS_CNTCTL_BASE |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 185 | |
| 186 | #if ERROR_DEPRECATED |
| 187 | unsigned int plat_get_syscnt_freq2(void) |
| 188 | { |
Sandrine Bailleux | a8ef665 | 2016-06-03 15:00:46 +0100 | [diff] [blame] | 189 | unsigned int counter_base_frequency; |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 190 | #else |
Yatharth Kochar | 3c0087a | 2016-04-14 14:49:37 +0100 | [diff] [blame] | 191 | unsigned long long plat_get_syscnt_freq(void) |
| 192 | { |
| 193 | unsigned long long counter_base_frequency; |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 194 | #endif /* ERROR_DEPRECATED */ |
Yatharth Kochar | 3c0087a | 2016-04-14 14:49:37 +0100 | [diff] [blame] | 195 | |
| 196 | /* Read the frequency from Frequency modes table */ |
| 197 | counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); |
| 198 | |
| 199 | /* The first entry of the frequency modes table must not be 0 */ |
| 200 | if (counter_base_frequency == 0) |
| 201 | panic(); |
| 202 | |
| 203 | return counter_base_frequency; |
| 204 | } |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 205 | |
Yatharth Kochar | 0b49fb7 | 2016-04-26 10:36:29 +0100 | [diff] [blame] | 206 | #endif /* ARM_SYS_CNTCTL_BASE */ |