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Soby Mathew991d42c2015-06-29 16:30:12 +01001/*
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Soby Mathew991d42c2015-06-29 16:30:12 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew991d42c2015-06-29 16:30:12 +01005 */
6
Soby Mathew991d42c2015-06-29 16:30:12 +01007#include <assert.h>
Soby Mathew991d42c2015-06-29 16:30:12 +01008#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch.h>
11#include <arch_helpers.h>
12#include <common/debug.h>
13#include <lib/pmf/pmf.h>
14#include <lib/runtime_instr.h>
15#include <plat/common/platform.h>
16
Soby Mathew991d42c2015-06-29 16:30:12 +010017#include "psci_private.h"
18
Soby Mathew6b8b3022015-06-30 11:00:24 +010019/******************************************************************************
Soby Mathew85dbf5a2015-04-07 12:16:56 +010020 * Construct the psci_power_state to request power OFF at all power levels.
21 ******************************************************************************/
22static void psci_set_power_off_state(psci_power_state_t *state_info)
23{
Varun Wadekar66231d12017-06-07 09:57:42 -070024 unsigned int lvl;
Soby Mathew85dbf5a2015-04-07 12:16:56 +010025
26 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++)
27 state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE;
28}
29
30/******************************************************************************
Soby Mathew991d42c2015-06-29 16:30:12 +010031 * Top level handler which is called when a cpu wants to power itself down.
Soby Mathew3a9e8bf2015-05-05 16:33:16 +010032 * It's assumed that along with turning the cpu power domain off, power
33 * domains at higher levels will be turned off as far as possible. It finds
34 * the highest level where a domain has to be powered off by traversing the
35 * node information and then performs generic, architectural, platform setup
36 * and state management required to turn OFF that power domain and domains
37 * below it. e.g. For a cpu that's to be powered OFF, it could mean programming
38 * the power controller whereas for a cluster that's to be powered off, it will
39 * call the platform specific code which will disable coherency at the
40 * interconnect level if the cpu is the last in the cluster and also the
41 * program the power controller.
Soby Mathew991d42c2015-06-29 16:30:12 +010042 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010043int psci_do_cpu_off(unsigned int end_pwrlvl)
Soby Mathew991d42c2015-06-29 16:30:12 +010044{
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010045 int rc = PSCI_E_SUCCESS;
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060046 unsigned int idx = plat_my_core_pos();
Soby Mathew85dbf5a2015-04-07 12:16:56 +010047 psci_power_state_t state_info;
Andrew F. Davis74e89782019-06-04 10:46:54 -040048 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
Soby Mathew991d42c2015-06-29 16:30:12 +010049
50 /*
51 * This function must only be called on platforms where the
52 * CPU_OFF platform hooks have been implemented.
53 */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010054 assert(psci_plat_pm_ops->pwr_domain_off != NULL);
Soby Mathew991d42c2015-06-29 16:30:12 +010055
Roberto Vargas3cb73cb2017-09-04 16:49:41 +010056 /* Construct the psci_power_state for CPU_OFF */
57 psci_set_power_off_state(&state_info);
58
Soby Mathew991d42c2015-06-29 16:30:12 +010059 /*
Andrew F. Davis74e89782019-06-04 10:46:54 -040060 * Get the parent nodes here, this is important to do before we
61 * initiate the power down sequence as after that point the core may
62 * have exited coherency and its cache may be disabled, any access to
63 * shared memory after that (such as the parent node lookup in
64 * psci_cpu_pd_nodes) can cause coherency issues on some platforms.
65 */
66 psci_get_parent_pwr_domain_nodes(idx, end_pwrlvl, parent_nodes);
67
68 /*
Soby Mathew3a9e8bf2015-05-05 16:33:16 +010069 * This function acquires the lock corresponding to each power
Soby Mathew991d42c2015-06-29 16:30:12 +010070 * level so that by the time all locks are taken, the system topology
71 * is snapshot and state management can be done safely.
72 */
Andrew F. Davis74e89782019-06-04 10:46:54 -040073 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes);
Soby Mathew991d42c2015-06-29 16:30:12 +010074
75 /*
76 * Call the cpu off handler registered by the Secure Payload Dispatcher
77 * to let it do any bookkeeping. Assume that the SPD always reports an
78 * E_DENIED error if SP refuse to power down
79 */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010080 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_off != NULL)) {
Soby Mathew991d42c2015-06-29 16:30:12 +010081 rc = psci_spd_pm->svc_off(0);
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010082 if (rc != 0)
Soby Mathew991d42c2015-06-29 16:30:12 +010083 goto exit;
84 }
85
86 /*
Soby Mathew85dbf5a2015-04-07 12:16:56 +010087 * This function is passed the requested state info and
88 * it returns the negotiated state info for each power level upto
89 * the end level specified.
Soby Mathew991d42c2015-06-29 16:30:12 +010090 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +010091 psci_do_state_coordination(end_pwrlvl, &state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +010092
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010093#if ENABLE_PSCI_STAT
94 /* Update the last cpu for each level till end_pwrlvl */
95 psci_stats_update_pwr_down(end_pwrlvl, &state_info);
96#endif
97
dp-arm2d92de62016-11-15 13:25:30 +000098#if ENABLE_RUNTIME_INSTRUMENTATION
99
100 /*
101 * Flush cache line so that even if CPU power down happens
102 * the timestamp update is reflected in memory.
103 */
104 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
105 RT_INSTR_ENTER_CFLUSH,
106 PMF_CACHE_MAINT);
107#endif
108
Soby Mathew6b8b3022015-06-30 11:00:24 +0100109 /*
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000110 * Arch. management. Initiate power down sequence.
Soby Mathew6b8b3022015-06-30 11:00:24 +0100111 */
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000112 psci_do_pwrdown_sequence(psci_find_max_off_lvl(&state_info));
Soby Mathew991d42c2015-06-29 16:30:12 +0100113
dp-arm2d92de62016-11-15 13:25:30 +0000114#if ENABLE_RUNTIME_INSTRUMENTATION
115 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
116 RT_INSTR_EXIT_CFLUSH,
117 PMF_NO_CACHE_MAINT);
118#endif
119
Soby Mathew991d42c2015-06-29 16:30:12 +0100120 /*
Soby Mathew6b8b3022015-06-30 11:00:24 +0100121 * Plat. management: Perform platform specific actions to turn this
122 * cpu off e.g. exit cpu coherency, program the power controller etc.
Soby Mathew991d42c2015-06-29 16:30:12 +0100123 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100124 psci_plat_pm_ops->pwr_domain_off(&state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100125
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100126#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +0000127 plat_psci_stat_accounting_start(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100128#endif
129
Soby Mathew991d42c2015-06-29 16:30:12 +0100130exit:
131 /*
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100132 * Release the locks corresponding to each power level in the
Soby Mathew991d42c2015-06-29 16:30:12 +0100133 * reverse order to which they were acquired.
134 */
Andrew F. Davis74e89782019-06-04 10:46:54 -0400135 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
Soby Mathew991d42c2015-06-29 16:30:12 +0100136
137 /*
Soby Mathew991d42c2015-06-29 16:30:12 +0100138 * Check if all actions needed to safely power down this cpu have
Soby Mathewd50e7d92015-10-01 16:46:06 +0100139 * successfully completed.
Soby Mathew991d42c2015-06-29 16:30:12 +0100140 */
Soby Mathewd50e7d92015-10-01 16:46:06 +0100141 if (rc == PSCI_E_SUCCESS) {
142 /*
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000143 * Set the affinity info state to OFF. When caches are disabled,
144 * this writes directly to main memory, so cache maintenance is
Soby Mathewd50e7d92015-10-01 16:46:06 +0100145 * required to ensure that later cached reads of aff_info_state
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000146 * return AFF_STATE_OFF. A dsbish() ensures ordering of the
Soby Mathewca370502016-01-26 11:47:53 +0000147 * update to the affinity info state prior to cache line
148 * invalidation.
Soby Mathewd50e7d92015-10-01 16:46:06 +0100149 */
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000150 psci_flush_cpu_data(psci_svc_cpu_data.aff_info_state);
Soby Mathewd50e7d92015-10-01 16:46:06 +0100151 psci_set_aff_info_state(AFF_STATE_OFF);
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000152 psci_dsbish();
153 psci_inv_cpu_data(psci_svc_cpu_data.aff_info_state);
Soby Mathewd50e7d92015-10-01 16:46:06 +0100154
dp-arm3cac7862016-09-19 11:18:44 +0100155#if ENABLE_RUNTIME_INSTRUMENTATION
156
157 /*
158 * Update the timestamp with cache off. We assume this
159 * timestamp can only be read from the current CPU and the
160 * timestamp cache line will be flushed before return to
161 * normal world on wakeup.
162 */
163 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
164 RT_INSTR_ENTER_HW_LOW_PWR,
165 PMF_NO_CACHE_MAINT);
166#endif
167
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100168 if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi != NULL) {
Soby Mathew6a816412016-04-27 14:46:28 +0100169 /* This function must not return */
170 psci_plat_pm_ops->pwr_domain_pwr_down_wfi(&state_info);
171 } else {
172 /*
173 * Enter a wfi loop which will allow the power
174 * controller to physically power down this cpu.
175 */
176 psci_power_down_wfi();
177 }
Soby Mathewd50e7d92015-10-01 16:46:06 +0100178 }
Soby Mathew991d42c2015-06-29 16:30:12 +0100179
180 return rc;
181}