Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <assert.h> |
| 34 | #include <debug.h> |
| 35 | #include <string.h> |
| 36 | #include "psci_private.h" |
| 37 | |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame] | 38 | /****************************************************************************** |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 39 | * Top level handler which is called when a cpu wants to power itself down. |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 40 | * It's assumed that along with turning the cpu power domain off, power |
| 41 | * domains at higher levels will be turned off as far as possible. It finds |
| 42 | * the highest level where a domain has to be powered off by traversing the |
| 43 | * node information and then performs generic, architectural, platform setup |
| 44 | * and state management required to turn OFF that power domain and domains |
| 45 | * below it. e.g. For a cpu that's to be powered OFF, it could mean programming |
| 46 | * the power controller whereas for a cluster that's to be powered off, it will |
| 47 | * call the platform specific code which will disable coherency at the |
| 48 | * interconnect level if the cpu is the last in the cluster and also the |
| 49 | * program the power controller. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 50 | ******************************************************************************/ |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 51 | int psci_do_cpu_off(int end_pwrlvl) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 52 | { |
| 53 | int rc; |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 54 | mpidr_pwr_map_nodes_t mpidr_nodes; |
| 55 | unsigned int max_phys_off_pwrlvl; |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 56 | |
| 57 | /* |
| 58 | * This function must only be called on platforms where the |
| 59 | * CPU_OFF platform hooks have been implemented. |
| 60 | */ |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 61 | assert(psci_plat_pm_ops->pwr_domain_off); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 62 | |
| 63 | /* |
| 64 | * Collect the pointers to the nodes in the topology tree for |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 65 | * each power domain instance in the mpidr. If this function does |
| 66 | * not return successfully then either the mpidr or the power |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 67 | * levels are incorrect. Either way, this an internal TF error |
| 68 | * therefore assert. |
| 69 | */ |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 70 | rc = psci_get_pwr_map_nodes(read_mpidr_el1() & MPIDR_AFFINITY_MASK, |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame] | 71 | MPIDR_AFFLVL0, |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 72 | end_pwrlvl, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 73 | mpidr_nodes); |
| 74 | assert(rc == PSCI_E_SUCCESS); |
| 75 | |
| 76 | /* |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 77 | * This function acquires the lock corresponding to each power |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 78 | * level so that by the time all locks are taken, the system topology |
| 79 | * is snapshot and state management can be done safely. |
| 80 | */ |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 81 | psci_acquire_pwr_domain_locks(MPIDR_AFFLVL0, |
| 82 | end_pwrlvl, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 83 | mpidr_nodes); |
| 84 | |
| 85 | |
| 86 | /* |
| 87 | * Call the cpu off handler registered by the Secure Payload Dispatcher |
| 88 | * to let it do any bookkeeping. Assume that the SPD always reports an |
| 89 | * E_DENIED error if SP refuse to power down |
| 90 | */ |
| 91 | if (psci_spd_pm && psci_spd_pm->svc_off) { |
| 92 | rc = psci_spd_pm->svc_off(0); |
| 93 | if (rc) |
| 94 | goto exit; |
| 95 | } |
| 96 | |
| 97 | /* |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 98 | * This function updates the state of each power domain instance |
| 99 | * corresponding to the mpidr in the range of power levels |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 100 | * specified. |
| 101 | */ |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 102 | psci_do_state_coordination(MPIDR_AFFLVL0, |
| 103 | end_pwrlvl, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 104 | mpidr_nodes, |
| 105 | PSCI_STATE_OFF); |
| 106 | |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 107 | max_phys_off_pwrlvl = psci_find_max_phys_off_pwrlvl(MPIDR_AFFLVL0, |
| 108 | end_pwrlvl, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 109 | mpidr_nodes); |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 110 | assert(max_phys_off_pwrlvl != PSCI_INVALID_DATA); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 111 | |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame] | 112 | /* |
| 113 | * Arch. management. Perform the necessary steps to flush all |
| 114 | * cpu caches. |
| 115 | */ |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 116 | psci_do_pwrdown_cache_maintenance(max_phys_off_pwrlvl); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 117 | |
| 118 | /* |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame] | 119 | * Plat. management: Perform platform specific actions to turn this |
| 120 | * cpu off e.g. exit cpu coherency, program the power controller etc. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 121 | */ |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 122 | psci_plat_pm_ops->pwr_domain_off(max_phys_off_pwrlvl); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 123 | |
| 124 | exit: |
| 125 | /* |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 126 | * Release the locks corresponding to each power level in the |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 127 | * reverse order to which they were acquired. |
| 128 | */ |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame^] | 129 | psci_release_pwr_domain_locks(MPIDR_AFFLVL0, |
| 130 | end_pwrlvl, |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 131 | mpidr_nodes); |
| 132 | |
| 133 | /* |
| 134 | * Check if all actions needed to safely power down this cpu have |
| 135 | * successfully completed. Enter a wfi loop which will allow the |
| 136 | * power controller to physically power down this cpu. |
| 137 | */ |
| 138 | if (rc == PSCI_E_SUCCESS) |
| 139 | psci_power_down_wfi(); |
| 140 | |
| 141 | return rc; |
| 142 | } |