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git01.mediatek.com / filogic / atf / ccd260070da1b4274ba038e57dd583db778c443b / . / plat / mediatek / mt8186 / include / platform_def.h
blob: 72fc0a672758e966e94023e09a97258f258515e9 [file] [log] [blame]
Rex-BC Chen749b2112021-09-28 11:24:09 +0800[diff] [blame]1/*
2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#define PLAT_PRIMARY_CPU 0x0
11
12#define MT_GIC_BASE (0x0C000000)
13#define MCUCFG_BASE (0x0C530000)
14#define IO_PHYS (0x10000000)
15
16/* Aggregate of all devices for MMU mapping */
17#define MTK_DEV_RNG0_BASE IO_PHYS
18#define MTK_DEV_RNG0_SIZE 0x400000
19#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000)
20#define MTK_DEV_RNG1_SIZE 0xa110000
21#define MTK_DEV_RNG2_BASE MT_GIC_BASE
22#define MTK_DEV_RNG2_SIZE 0x600000
23
24
25/*******************************************************************************
26 * UART related constants
27 ******************************************************************************/
28#define UART0_BASE (IO_PHYS + 0x01002000)
29
30#define UART_BAUDRATE 115200
31
32/*******************************************************************************
James Lo4ac7a412021-10-06 18:12:30 +0800[diff] [blame]33 * PWRAP related constants
34 ******************************************************************************/
35#define PMIC_WRAP_BASE (IO_PHYS + 0x0000D000)
36
37/*******************************************************************************
Penny Janfb70fb42021-10-03 10:11:04 +0800[diff] [blame]38 * EMI MPU related constants
39 ******************************************************************************/
40#define EMI_MPU_BASE (IO_PHYS + 0x0021B000)
41
42/*******************************************************************************
Christine Zhuccd26002021-10-11 21:29:58 +0800[diff] [blame^]43 * GIC-600 & interrupt handling related constants
44 ******************************************************************************/
45/* Base MTK_platform compatible GIC memory map */
46#define BASE_GICD_BASE MT_GIC_BASE
47#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
48
49/*******************************************************************************
Rex-BC Chen749b2112021-09-28 11:24:09 +0800[diff] [blame]50 * System counter frequency related constants
51 ******************************************************************************/
52#define SYS_COUNTER_FREQ_IN_TICKS 13000000
53#define SYS_COUNTER_FREQ_IN_MHZ 13
54
55/*******************************************************************************
56 * Platform binary types for linking
57 ******************************************************************************/
58#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
59#define PLATFORM_LINKER_ARCH aarch64
60
61/*******************************************************************************
62 * Generic platform constants
63 ******************************************************************************/
64#define PLATFORM_STACK_SIZE 0x800
65
66#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
67
68#define PLAT_MAX_PWR_LVL U(3)
69#define PLAT_MAX_RET_STATE U(1)
70#define PLAT_MAX_OFF_STATE U(9)
71
72#define PLATFORM_SYSTEM_COUNT U(1)
73#define PLATFORM_MCUSYS_COUNT U(1)
74#define PLATFORM_CLUSTER_COUNT U(1)
75#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
76#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
77
78#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
79#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8)
80
81#define SOC_CHIP_ID U(0x8186)
82
83/*******************************************************************************
84 * Platform memory map related constants
85 ******************************************************************************/
86#define TZRAM_BASE 0x54600000
87#define TZRAM_SIZE 0x00030000
88
89/*******************************************************************************
90 * BL31 specific defines.
91 ******************************************************************************/
92/*
93 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
94 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
95 * little space for growth.
96 */
97#define BL31_BASE (TZRAM_BASE + 0x1000)
98#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
99
100/*******************************************************************************
101 * Platform specific page table and MMU setup constants
102 ******************************************************************************/
103#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
104#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
105#define MAX_XLAT_TABLES 16
106#define MAX_MMAP_REGIONS 16
107
108/*******************************************************************************
109 * Declarations and constants to access the mailboxes safely. Each mailbox is
110 * aligned on the biggest cache line size in the platform. This is known only
111 * to the platform as it might have a combination of integrated and external
112 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
113 * line at any cache level. They could belong to different cpus/clusters &
114 * get written while being protected by different locks causing corruption of
115 * a valid mailbox address.
116 ******************************************************************************/
117#define CACHE_WRITEBACK_SHIFT 6
118#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
119#endif /* PLATFORM_DEF_H */