Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 1 | /* |
Daniel Boulby | 928747f | 2021-05-25 18:09:34 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef EL3_COMMON_MACROS_S |
| 8 | #define EL3_COMMON_MACROS_S |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 9 | |
| 10 | #include <arch.h> |
| 11 | #include <asm_macros.S> |
Daniel Boulby | 928747f | 2021-05-25 18:09:34 +0100 | [diff] [blame] | 12 | #include <assert_macros.S> |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 13 | #include <context.h> |
Varun Wadekar | 5dc9e9c | 2020-05-16 20:59:30 -0700 | [diff] [blame] | 14 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 15 | |
| 16 | /* |
| 17 | * Helper macro to initialise EL3 registers we care about. |
| 18 | */ |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 19 | .macro el3_arch_init_common |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 20 | /* --------------------------------------------------------------------- |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 21 | * SCTLR_EL3 has already been initialised - read current value before |
| 22 | * modifying. |
| 23 | * |
| 24 | * SCTLR_EL3.I: Enable the instruction cache. |
| 25 | * |
Qixiang Xu | 3cc3917 | 2018-03-05 09:31:11 +0800 | [diff] [blame] | 26 | * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 27 | * exception is generated if a load or store instruction executed at |
| 28 | * EL3 uses the SP as the base address and the SP is not aligned to a |
| 29 | * 16-byte boundary. |
| 30 | * |
| 31 | * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that |
| 32 | * load or store one or more registers have an alignment check that the |
| 33 | * address being accessed is aligned to the size of the data element(s) |
| 34 | * being accessed. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 35 | * --------------------------------------------------------------------- |
| 36 | */ |
| 37 | mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) |
| 38 | mrs x0, sctlr_el3 |
| 39 | orr x0, x0, x1 |
| 40 | msr sctlr_el3, x0 |
| 41 | isb |
| 42 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 43 | #ifdef IMAGE_BL31 |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 44 | /* --------------------------------------------------------------------- |
| 45 | * Initialise the per-cpu cache pointer to the CPU. |
| 46 | * This is done early to enable crash reporting to have access to crash |
| 47 | * stack. Since crash reporting depends on cpu_data to report the |
| 48 | * unhandled exception, not doing so can lead to recursive exceptions |
| 49 | * due to a NULL TPIDR_EL3. |
| 50 | * --------------------------------------------------------------------- |
| 51 | */ |
| 52 | bl init_cpu_data_ptr |
| 53 | #endif /* IMAGE_BL31 */ |
| 54 | |
| 55 | /* --------------------------------------------------------------------- |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 56 | * Initialise SCR_EL3, setting all fields rather than relying on hw. |
| 57 | * All fields are architecturally UNKNOWN on reset. The following fields |
| 58 | * do not change during the TF lifetime. The remaining fields are set to |
| 59 | * zero here but are updated ahead of transitioning to a lower EL in the |
| 60 | * function cm_init_context_common(). |
| 61 | * |
| 62 | * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at |
| 63 | * EL2, EL1 and EL0 are not trapped to EL3. |
| 64 | * |
| 65 | * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at |
| 66 | * EL2, EL1 and EL0 are not trapped to EL3. |
| 67 | * |
| 68 | * SCR_EL3.SIF: Set to one to disable instruction fetches from |
| 69 | * Non-secure memory. |
| 70 | * |
| 71 | * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from |
| 72 | * both Security states and both Execution states. |
| 73 | * |
| 74 | * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts |
| 75 | * to EL3 when executing at any EL. |
Jeenu Viswambharan | cbad661 | 2018-08-15 14:29:29 +0100 | [diff] [blame] | 76 | * |
| 77 | * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, |
| 78 | * disable traps to EL3 when accessing key registers or using pointer |
| 79 | * authentication instructions from lower ELs. |
Gerald Lejeune | 632d6df | 2016-03-22 09:29:23 +0100 | [diff] [blame] | 80 | * --------------------------------------------------------------------- |
| 81 | */ |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 82 | mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 83 | & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 84 | #if CTX_INCLUDE_PAUTH_REGS |
| 85 | /* |
| 86 | * If the pointer authentication registers are saved during world |
| 87 | * switches, enable pointer authentication everywhere, as it is safe to |
| 88 | * do so. |
| 89 | */ |
| 90 | orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) |
| 91 | #endif |
Zelalem Aweke | 688fbf7 | 2021-07-09 11:37:10 -0500 | [diff] [blame] | 92 | #if ENABLE_RME |
| 93 | /* |
| 94 | * TODO: Settting the EEL2 bit to allow EL3 access to secure only registers |
| 95 | * in context management. This will need to be refactored. |
| 96 | */ |
| 97 | orr x0, x0, #SCR_EEL2_BIT |
| 98 | #endif |
Gerald Lejeune | 632d6df | 2016-03-22 09:29:23 +0100 | [diff] [blame] | 99 | msr scr_el3, x0 |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 100 | |
| 101 | /* --------------------------------------------------------------------- |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 102 | * Initialise MDCR_EL3, setting all fields rather than relying on hw. |
| 103 | * Some fields are architecturally UNKNOWN on reset. |
| 104 | * |
| 105 | * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. |
| 106 | * Debug exceptions, other than Breakpoint Instruction exceptions, are |
| 107 | * disabled from all ELs in Secure state. |
| 108 | * |
| 109 | * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted |
| 110 | * privileged debug from S-EL1. |
| 111 | * |
| 112 | * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register |
| 113 | * access to the powerdown debug registers do not trap to EL3. |
| 114 | * |
| 115 | * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the |
| 116 | * debug registers, other than those registers that are controlled by |
| 117 | * MDCR_EL3.TDOSA. |
| 118 | * |
| 119 | * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register |
| 120 | * accesses to all Performance Monitors registers do not trap to EL3. |
Antonio Nino Diaz | 3fbd3f5 | 2019-02-18 16:55:43 +0000 | [diff] [blame] | 121 | * |
| 122 | * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is |
| 123 | * prohibited in Secure state. This bit is RES0 in versions of the |
Alexei Fedorov | 307f34b | 2021-05-14 11:21:56 +0100 | [diff] [blame] | 124 | * architecture with FEAT_PMUv3p5 not implemented, setting it to 1 |
| 125 | * doesn't have any effect on them. |
| 126 | * |
| 127 | * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is |
| 128 | * prohibited in EL3. This bit is RES0 in versions of the |
| 129 | * architecture with FEAT_PMUv3p7 not implemented, setting it to 1 |
| 130 | * doesn't have any effect on them. |
Petre-Ionut Tudor | add24a4 | 2019-10-03 17:09:08 +0100 | [diff] [blame] | 131 | * |
| 132 | * MDCR_EL3.SPME: Set to zero so that event counting by the programmable |
| 133 | * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 |
| 134 | * Debug is not implemented this bit does not have any effect on the |
| 135 | * counters unless there is support for the implementation defined |
| 136 | * authentication interface ExternalSecureNoninvasiveDebugEnabled(). |
Manish V Badarkhe | e1cccb4 | 2021-06-23 20:02:39 +0100 | [diff] [blame] | 137 | * |
| 138 | * MDCR_EL3.NSTB, MDCR_EL3.NSTBE: Set to zero so that Trace Buffer |
| 139 | * owning security state is Secure state. If FEAT_TRBE is implemented, |
| 140 | * accesses to Trace Buffer control registers at EL2 and EL1 in any |
| 141 | * security state generates trap exceptions to EL3. |
| 142 | * If FEAT_TRBE is not implemented, these bits are RES0. |
Manish V Badarkhe | 8ce3394 | 2021-07-18 02:26:27 +0100 | [diff] [blame] | 143 | * |
| 144 | * MDCR_EL3.TTRF: Set to one so that access to trace filter control |
| 145 | * registers in non-monitor mode generate EL3 trap exception, |
| 146 | * unless the access generates a higher priority exception when trace |
| 147 | * filter control(FEAT_TRF) is implemented. |
| 148 | * When FEAT_TRF is not implemented, this bit is RES0. |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 149 | * --------------------------------------------------------------------- |
| 150 | */ |
Antonio Nino Diaz | 3fbd3f5 | 2019-02-18 16:55:43 +0000 | [diff] [blame] | 151 | mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ |
Alexei Fedorov | 307f34b | 2021-05-14 11:21:56 +0100 | [diff] [blame] | 152 | MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \ |
| 153 | MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \ |
Manish V Badarkhe | e1cccb4 | 2021-06-23 20:02:39 +0100 | [diff] [blame] | 154 | MDCR_TDA_BIT | MDCR_TPM_BIT | MDCR_NSTB(MDCR_NSTB_EL1) | \ |
Manish V Badarkhe | 8ce3394 | 2021-07-18 02:26:27 +0100 | [diff] [blame] | 155 | MDCR_NSTBE | MDCR_TTRF_BIT)) |
Antonio Nino Diaz | 3fbd3f5 | 2019-02-18 16:55:43 +0000 | [diff] [blame] | 156 | |
Manish V Badarkhe | 8ce3394 | 2021-07-18 02:26:27 +0100 | [diff] [blame] | 157 | mrs x1, id_aa64dfr0_el1 |
| 158 | ubfx x1, x1, #ID_AA64DFR0_TRACEFILT_SHIFT, #ID_AA64DFR0_TRACEFILT_LENGTH |
| 159 | cbz x1, 1f |
| 160 | orr x0, x0, #MDCR_TTRF_BIT |
| 161 | 1: |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 162 | msr mdcr_el3, x0 |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 163 | |
Gerald Lejeune | 632d6df | 2016-03-22 09:29:23 +0100 | [diff] [blame] | 164 | /* --------------------------------------------------------------------- |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 165 | * Initialise PMCR_EL0 setting all fields rather than relying |
| 166 | * on hw. Some fields are architecturally UNKNOWN on reset. |
| 167 | * |
| 168 | * PMCR_EL0.LP: Set to one so that event counter overflow, that |
| 169 | * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment |
| 170 | * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU |
| 171 | * is implemented. This bit is RES0 in versions of the architecture |
| 172 | * earlier than ARMv8.5, setting it to 1 doesn't have any effect |
| 173 | * on them. |
| 174 | * |
| 175 | * PMCR_EL0.LC: Set to one so that cycle counter overflow, that |
| 176 | * is recorded in PMOVSCLR_EL0[31], occurs on the increment |
| 177 | * that changes PMCCNTR_EL0[63] from 1 to 0. |
| 178 | * |
| 179 | * PMCR_EL0.DP: Set to one so that the cycle counter, |
| 180 | * PMCCNTR_EL0 does not count when event counting is prohibited. |
| 181 | * |
| 182 | * PMCR_EL0.X: Set to zero to disable export of events. |
| 183 | * |
| 184 | * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 |
| 185 | * counts on every clock cycle. |
| 186 | * --------------------------------------------------------------------- |
| 187 | */ |
| 188 | mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ |
| 189 | PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ |
| 190 | ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) |
| 191 | |
| 192 | msr pmcr_el0, x0 |
| 193 | |
| 194 | /* --------------------------------------------------------------------- |
Gerald Lejeune | 632d6df | 2016-03-22 09:29:23 +0100 | [diff] [blame] | 195 | * Enable External Aborts and SError Interrupts now that the exception |
| 196 | * vectors have been setup. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 197 | * --------------------------------------------------------------------- |
| 198 | */ |
| 199 | msr daifclr, #DAIF_ABT_BIT |
| 200 | |
| 201 | /* --------------------------------------------------------------------- |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 202 | * Initialise CPTR_EL3, setting all fields rather than relying on hw. |
| 203 | * All fields are architecturally UNKNOWN on reset. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 204 | * |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 205 | * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, |
| 206 | * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 207 | * |
Manish V Badarkhe | f7ee064 | 2021-07-07 16:27:10 +0100 | [diff] [blame] | 208 | * CPTR_EL3.TTA: Set to one so that accesses to the trace system |
| 209 | * registers trap to EL3 from all exception levels and security |
| 210 | * states when system register trace is implemented. |
| 211 | * When system register trace is not implemented, this bit is RES0 and |
| 212 | * hence set to zero. |
| 213 | * |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 214 | * CPTR_EL3.TTA: Set to zero so that System register accesses to the |
| 215 | * trace registers do not trap to EL3. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 216 | * |
David Cunado | ce88eee | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 217 | * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers |
| 218 | * by Advanced SIMD, floating-point or SVE instructions (if implemented) |
| 219 | * do not trap to EL3. |
Max Shvetsov | c450277 | 2021-03-22 11:59:37 +0000 | [diff] [blame] | 220 | * |
| 221 | * CPTR_EL3.TAM: Set to one so that Activity Monitor access is |
| 222 | * trapped to EL3 by default. |
| 223 | * |
| 224 | * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped |
| 225 | * to EL3 by default. |
johpow01 | 9baade3 | 2021-07-08 14:14:00 -0500 | [diff] [blame] | 226 | * |
| 227 | * CPTR_EL3.ESM: Set to zero so that all SME functionality is trapped |
| 228 | * to EL3 by default. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 229 | */ |
Max Shvetsov | c450277 | 2021-03-22 11:59:37 +0000 | [diff] [blame] | 230 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 231 | mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) |
Manish V Badarkhe | f7ee064 | 2021-07-07 16:27:10 +0100 | [diff] [blame] | 232 | mrs x1, id_aa64dfr0_el1 |
| 233 | ubfx x1, x1, #ID_AA64DFR0_TRACEVER_SHIFT, #ID_AA64DFR0_TRACEVER_LENGTH |
| 234 | cbz x1, 1f |
| 235 | orr x0, x0, #TTA_BIT |
| 236 | 1: |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 237 | msr cptr_el3, x0 |
Sathees Balya | 0911df1 | 2018-12-06 13:33:24 +0000 | [diff] [blame] | 238 | |
| 239 | /* |
| 240 | * If Data Independent Timing (DIT) functionality is implemented, |
Daniel Boulby | 928747f | 2021-05-25 18:09:34 +0100 | [diff] [blame] | 241 | * always enable DIT in EL3. |
| 242 | * First assert that the FEAT_DIT build flag matches the feature id |
| 243 | * register value for DIT. |
Sathees Balya | 0911df1 | 2018-12-06 13:33:24 +0000 | [diff] [blame] | 244 | */ |
Daniel Boulby | 928747f | 2021-05-25 18:09:34 +0100 | [diff] [blame] | 245 | #if ENABLE_FEAT_DIT |
| 246 | #if ENABLE_ASSERTIONS |
Sathees Balya | 0911df1 | 2018-12-06 13:33:24 +0000 | [diff] [blame] | 247 | mrs x0, id_aa64pfr0_el1 |
| 248 | ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH |
| 249 | cmp x0, #ID_AA64PFR0_DIT_SUPPORTED |
Daniel Boulby | 928747f | 2021-05-25 18:09:34 +0100 | [diff] [blame] | 250 | ASM_ASSERT(eq) |
| 251 | #endif /* ENABLE_ASSERTIONS */ |
Sathees Balya | 0911df1 | 2018-12-06 13:33:24 +0000 | [diff] [blame] | 252 | mov x0, #DIT_BIT |
| 253 | msr DIT, x0 |
Daniel Boulby | 928747f | 2021-05-25 18:09:34 +0100 | [diff] [blame] | 254 | #endif |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 255 | .endm |
| 256 | |
| 257 | /* ----------------------------------------------------------------------------- |
| 258 | * This is the super set of actions that need to be performed during a cold boot |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 259 | * or a warm boot in EL3. This code is shared by BL1 and BL31. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 260 | * |
| 261 | * This macro will always perform reset handling, architectural initialisations |
| 262 | * and stack setup. The rest of the actions are optional because they might not |
| 263 | * be needed, depending on the context in which this macro is called. This is |
| 264 | * why this macro is parameterised ; each parameter allows to enable/disable |
| 265 | * some actions. |
| 266 | * |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 267 | * _init_sctlr: |
| 268 | * Whether the macro needs to initialise SCTLR_EL3, including configuring |
| 269 | * the endianness of data accesses. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 270 | * |
| 271 | * _warm_boot_mailbox: |
| 272 | * Whether the macro needs to detect the type of boot (cold/warm). The |
| 273 | * detection is based on the platform entrypoint address : if it is zero |
| 274 | * then it is a cold boot, otherwise it is a warm boot. In the latter case, |
| 275 | * this macro jumps on the platform entrypoint address. |
| 276 | * |
| 277 | * _secondary_cold_boot: |
| 278 | * Whether the macro needs to identify the CPU that is calling it: primary |
| 279 | * CPU or secondary CPU. The primary CPU will be allowed to carry on with |
| 280 | * the platform initialisations, while the secondaries will be put in a |
| 281 | * platform-specific state in the meantime. |
| 282 | * |
| 283 | * If the caller knows this macro will only be called by the primary CPU |
| 284 | * then this parameter can be defined to 0 to skip this step. |
| 285 | * |
| 286 | * _init_memory: |
| 287 | * Whether the macro needs to initialise the memory. |
| 288 | * |
| 289 | * _init_c_runtime: |
| 290 | * Whether the macro needs to initialise the C runtime environment. |
| 291 | * |
| 292 | * _exception_vectors: |
| 293 | * Address of the exception vectors to program in the VBAR_EL3 register. |
Manish Pandey | c825768 | 2019-11-26 11:34:17 +0000 | [diff] [blame] | 294 | * |
| 295 | * _pie_fixup_size: |
| 296 | * Size of memory region to fixup Global Descriptor Table (GDT). |
| 297 | * |
| 298 | * A non-zero value is expected when firmware needs GDT to be fixed-up. |
| 299 | * |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 300 | * ----------------------------------------------------------------------------- |
| 301 | */ |
| 302 | .macro el3_entrypoint_common \ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 303 | _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \ |
Manish Pandey | c825768 | 2019-11-26 11:34:17 +0000 | [diff] [blame] | 304 | _init_memory, _init_c_runtime, _exception_vectors, \ |
| 305 | _pie_fixup_size |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 306 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 307 | .if \_init_sctlr |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 308 | /* ------------------------------------------------------------- |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 309 | * This is the initialisation of SCTLR_EL3 and so must ensure |
| 310 | * that all fields are explicitly set rather than relying on hw. |
| 311 | * Some fields reset to an IMPLEMENTATION DEFINED value and |
| 312 | * others are architecturally UNKNOWN on reset. |
| 313 | * |
| 314 | * SCTLR.EE: Set the CPU endianness before doing anything that |
| 315 | * might involve memory reads or writes. Set to zero to select |
| 316 | * Little Endian. |
| 317 | * |
| 318 | * SCTLR_EL3.WXN: For the EL3 translation regime, this field can |
| 319 | * force all memory regions that are writeable to be treated as |
| 320 | * XN (Execute-never). Set to zero so that this control has no |
| 321 | * effect on memory access permissions. |
| 322 | * |
Qixiang Xu | 3cc3917 | 2018-03-05 09:31:11 +0800 | [diff] [blame] | 323 | * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check. |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 324 | * |
| 325 | * SCTLR_EL3.A: Set to zero to disable Alignment fault checking. |
Jeenu Viswambharan | aa00aff | 2018-11-15 11:38:03 +0000 | [diff] [blame] | 326 | * |
| 327 | * SCTLR.DSSBS: Set to zero to disable speculation store bypass |
| 328 | * safe behaviour upon exception entry to EL3. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 329 | * ------------------------------------------------------------- |
| 330 | */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 331 | mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ |
Jeenu Viswambharan | aa00aff | 2018-11-15 11:38:03 +0000 | [diff] [blame] | 332 | | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 333 | msr sctlr_el3, x0 |
| 334 | isb |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 335 | .endif /* _init_sctlr */ |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 336 | |
Javier Almansa Sobrino | f3a4c54 | 2020-11-23 18:38:15 +0000 | [diff] [blame] | 337 | #if DISABLE_MTPMU |
| 338 | bl mtpmu_disable |
| 339 | #endif |
| 340 | |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 341 | .if \_warm_boot_mailbox |
| 342 | /* ------------------------------------------------------------- |
| 343 | * This code will be executed for both warm and cold resets. |
| 344 | * Now is the time to distinguish between the two. |
| 345 | * Query the platform entrypoint address and if it is not zero |
| 346 | * then it means it is a warm boot so jump to this address. |
| 347 | * ------------------------------------------------------------- |
| 348 | */ |
Soby Mathew | 3700a92 | 2015-07-13 11:21:11 +0100 | [diff] [blame] | 349 | bl plat_get_my_entrypoint |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 350 | cbz x0, do_cold_boot |
| 351 | br x0 |
| 352 | |
| 353 | do_cold_boot: |
| 354 | .endif /* _warm_boot_mailbox */ |
| 355 | |
Manish Pandey | c825768 | 2019-11-26 11:34:17 +0000 | [diff] [blame] | 356 | .if \_pie_fixup_size |
| 357 | #if ENABLE_PIE |
| 358 | /* |
| 359 | * ------------------------------------------------------------ |
| 360 | * If PIE is enabled fixup the Global descriptor Table only |
| 361 | * once during primary core cold boot path. |
| 362 | * |
| 363 | * Compile time base address, required for fixup, is calculated |
| 364 | * using "pie_fixup" label present within first page. |
| 365 | * ------------------------------------------------------------ |
| 366 | */ |
| 367 | pie_fixup: |
| 368 | ldr x0, =pie_fixup |
Jimmy Brisson | ed20207 | 2020-08-04 16:18:52 -0500 | [diff] [blame] | 369 | and x0, x0, #~(PAGE_SIZE_MASK) |
Manish Pandey | c825768 | 2019-11-26 11:34:17 +0000 | [diff] [blame] | 370 | mov_imm x1, \_pie_fixup_size |
| 371 | add x1, x1, x0 |
| 372 | bl fixup_gdt_reloc |
| 373 | #endif /* ENABLE_PIE */ |
| 374 | .endif /* _pie_fixup_size */ |
| 375 | |
Antonio Nino Diaz | 4357b41 | 2016-02-23 12:04:58 +0000 | [diff] [blame] | 376 | /* --------------------------------------------------------------------- |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 377 | * Set the exception vectors. |
| 378 | * --------------------------------------------------------------------- |
| 379 | */ |
| 380 | adr x0, \_exception_vectors |
| 381 | msr vbar_el3, x0 |
| 382 | isb |
| 383 | |
Zelalem Aweke | 688fbf7 | 2021-07-09 11:37:10 -0500 | [diff] [blame] | 384 | #if !(defined(IMAGE_BL2) && ENABLE_RME) |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 385 | /* --------------------------------------------------------------------- |
Antonio Nino Diaz | 4357b41 | 2016-02-23 12:04:58 +0000 | [diff] [blame] | 386 | * It is a cold boot. |
| 387 | * Perform any processor specific actions upon reset e.g. cache, TLB |
| 388 | * invalidations etc. |
| 389 | * --------------------------------------------------------------------- |
| 390 | */ |
| 391 | bl reset_handler |
Zelalem Aweke | 688fbf7 | 2021-07-09 11:37:10 -0500 | [diff] [blame] | 392 | #endif |
Antonio Nino Diaz | 4357b41 | 2016-02-23 12:04:58 +0000 | [diff] [blame] | 393 | |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 394 | el3_arch_init_common |
Antonio Nino Diaz | 4357b41 | 2016-02-23 12:04:58 +0000 | [diff] [blame] | 395 | |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 396 | .if \_secondary_cold_boot |
| 397 | /* ------------------------------------------------------------- |
Antonio Nino Diaz | 4357b41 | 2016-02-23 12:04:58 +0000 | [diff] [blame] | 398 | * Check if this is a primary or secondary CPU cold boot. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 399 | * The primary CPU will set up the platform while the |
| 400 | * secondaries are placed in a platform-specific state until the |
| 401 | * primary CPU performs the necessary actions to bring them out |
| 402 | * of that state and allows entry into the OS. |
| 403 | * ------------------------------------------------------------- |
| 404 | */ |
Soby Mathew | 3700a92 | 2015-07-13 11:21:11 +0100 | [diff] [blame] | 405 | bl plat_is_my_cpu_primary |
Soby Mathew | eb3bbf1 | 2015-06-08 12:32:50 +0100 | [diff] [blame] | 406 | cbnz w0, do_primary_cold_boot |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 407 | |
| 408 | /* This is a cold boot on a secondary CPU */ |
| 409 | bl plat_secondary_cold_boot_setup |
| 410 | /* plat_secondary_cold_boot_setup() is not supposed to return */ |
Antonio Nino Diaz | 1f21bcf | 2016-02-01 13:57:25 +0000 | [diff] [blame] | 411 | bl el3_panic |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 412 | |
| 413 | do_primary_cold_boot: |
| 414 | .endif /* _secondary_cold_boot */ |
| 415 | |
| 416 | /* --------------------------------------------------------------------- |
Antonio Nino Diaz | 4357b41 | 2016-02-23 12:04:58 +0000 | [diff] [blame] | 417 | * Initialize memory now. Secondary CPU initialization won't get to this |
| 418 | * point. |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 419 | * --------------------------------------------------------------------- |
| 420 | */ |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 421 | |
| 422 | .if \_init_memory |
| 423 | bl platform_mem_init |
| 424 | .endif /* _init_memory */ |
| 425 | |
| 426 | /* --------------------------------------------------------------------- |
| 427 | * Init C runtime environment: |
| 428 | * - Zero-initialise the NOBITS sections. There are 2 of them: |
| 429 | * - the .bss section; |
| 430 | * - the coherent memory section (if any). |
| 431 | * - Relocate the data section from ROM to RAM, if required. |
| 432 | * --------------------------------------------------------------------- |
| 433 | */ |
| 434 | .if \_init_c_runtime |
Zelalem Aweke | 688fbf7 | 2021-07-09 11:37:10 -0500 | [diff] [blame] | 435 | #if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \ |
| 436 | ((BL2_AT_EL3 && BL2_INV_DCACHE) || ENABLE_RME)) |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 437 | /* ------------------------------------------------------------- |
| 438 | * Invalidate the RW memory used by the BL31 image. This |
| 439 | * includes the data and NOBITS sections. This is done to |
| 440 | * safeguard against possible corruption of this memory by |
| 441 | * dirty cache lines in a system cache as a result of use by |
Zelalem Aweke | b0d69e8 | 2021-10-15 17:25:52 -0500 | [diff] [blame] | 442 | * an earlier boot loader stage. If PIE is enabled however, |
| 443 | * RO sections including the GOT may be modified during |
| 444 | * pie fixup. Therefore, to be on the safe side, invalidate |
| 445 | * the entire image region if PIE is enabled. |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 446 | * ------------------------------------------------------------- |
| 447 | */ |
Zelalem Aweke | b0d69e8 | 2021-10-15 17:25:52 -0500 | [diff] [blame] | 448 | #if ENABLE_PIE |
| 449 | #if SEPARATE_CODE_AND_RODATA |
| 450 | adrp x0, __TEXT_START__ |
| 451 | add x0, x0, :lo12:__TEXT_START__ |
| 452 | #else |
| 453 | adrp x0, __RO_START__ |
| 454 | add x0, x0, :lo12:__RO_START__ |
| 455 | #endif /* SEPARATE_CODE_AND_RODATA */ |
| 456 | #else |
Soby Mathew | fcaf1bd | 2018-10-12 16:40:28 +0100 | [diff] [blame] | 457 | adrp x0, __RW_START__ |
| 458 | add x0, x0, :lo12:__RW_START__ |
Zelalem Aweke | b0d69e8 | 2021-10-15 17:25:52 -0500 | [diff] [blame] | 459 | #endif /* ENABLE_PIE */ |
Soby Mathew | fcaf1bd | 2018-10-12 16:40:28 +0100 | [diff] [blame] | 460 | adrp x1, __RW_END__ |
| 461 | add x1, x1, :lo12:__RW_END__ |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 462 | sub x1, x1, x0 |
| 463 | bl inv_dcache_range |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 464 | #if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION |
| 465 | adrp x0, __NOBITS_START__ |
| 466 | add x0, x0, :lo12:__NOBITS_START__ |
| 467 | adrp x1, __NOBITS_END__ |
| 468 | add x1, x1, :lo12:__NOBITS_END__ |
| 469 | sub x1, x1, x0 |
| 470 | bl inv_dcache_range |
| 471 | #endif |
Jiafei Pan | 0824b45 | 2022-02-24 10:47:33 +0800 | [diff] [blame] | 472 | #if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION |
| 473 | adrp x0, __BL2_NOLOAD_START__ |
| 474 | add x0, x0, :lo12:__BL2_NOLOAD_START__ |
| 475 | adrp x1, __BL2_NOLOAD_END__ |
| 476 | add x1, x1, :lo12:__BL2_NOLOAD_END__ |
| 477 | sub x1, x1, x0 |
| 478 | bl inv_dcache_range |
| 479 | #endif |
Roberto Vargas | e0e9946 | 2017-10-30 14:43:43 +0000 | [diff] [blame] | 480 | #endif |
Soby Mathew | fcaf1bd | 2018-10-12 16:40:28 +0100 | [diff] [blame] | 481 | adrp x0, __BSS_START__ |
| 482 | add x0, x0, :lo12:__BSS_START__ |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 483 | |
Soby Mathew | fcaf1bd | 2018-10-12 16:40:28 +0100 | [diff] [blame] | 484 | adrp x1, __BSS_END__ |
| 485 | add x1, x1, :lo12:__BSS_END__ |
| 486 | sub x1, x1, x0 |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 487 | bl zeromem |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 488 | |
| 489 | #if USE_COHERENT_MEM |
Soby Mathew | fcaf1bd | 2018-10-12 16:40:28 +0100 | [diff] [blame] | 490 | adrp x0, __COHERENT_RAM_START__ |
| 491 | add x0, x0, :lo12:__COHERENT_RAM_START__ |
| 492 | adrp x1, __COHERENT_RAM_END_UNALIGNED__ |
| 493 | add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__ |
| 494 | sub x1, x1, x0 |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 495 | bl zeromem |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 496 | #endif |
| 497 | |
Lionel Debieve | d2f21b8 | 2019-05-27 09:32:00 +0200 | [diff] [blame] | 498 | #if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) |
Soby Mathew | fcaf1bd | 2018-10-12 16:40:28 +0100 | [diff] [blame] | 499 | adrp x0, __DATA_RAM_START__ |
| 500 | add x0, x0, :lo12:__DATA_RAM_START__ |
| 501 | adrp x1, __DATA_ROM_START__ |
| 502 | add x1, x1, :lo12:__DATA_ROM_START__ |
| 503 | adrp x2, __DATA_RAM_END__ |
| 504 | add x2, x2, :lo12:__DATA_RAM_END__ |
| 505 | sub x2, x2, x0 |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 506 | bl memcpy16 |
| 507 | #endif |
| 508 | .endif /* _init_c_runtime */ |
| 509 | |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 510 | /* --------------------------------------------------------------------- |
| 511 | * Use SP_EL0 for the C runtime stack. |
| 512 | * --------------------------------------------------------------------- |
| 513 | */ |
| 514 | msr spsel, #0 |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 515 | |
| 516 | /* --------------------------------------------------------------------- |
| 517 | * Allocate a stack whose memory will be marked as Normal-IS-WBWA when |
| 518 | * the MMU is enabled. There is no risk of reading stale stack memory |
| 519 | * after enabling the MMU as only the primary CPU is running at the |
| 520 | * moment. |
| 521 | * --------------------------------------------------------------------- |
| 522 | */ |
Soby Mathew | 3700a92 | 2015-07-13 11:21:11 +0100 | [diff] [blame] | 523 | bl plat_set_my_stack |
Douglas Raillard | 306593d | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 524 | |
| 525 | #if STACK_PROTECTOR_ENABLED |
| 526 | .if \_init_c_runtime |
| 527 | bl update_stack_protector_canary |
| 528 | .endif /* _init_c_runtime */ |
| 529 | #endif |
Sandrine Bailleux | acde8b0 | 2015-05-19 11:54:45 +0100 | [diff] [blame] | 530 | .endm |
| 531 | |
Manish V Badarkhe | e07e808 | 2020-07-23 12:43:25 +0100 | [diff] [blame] | 532 | .macro apply_at_speculative_wa |
| 533 | #if ERRATA_SPECULATIVE_AT |
| 534 | /* |
| 535 | * Explicitly save x30 so as to free up a register and to enable |
| 536 | * branching and also, save x29 which will be used in the called |
| 537 | * function |
| 538 | */ |
| 539 | stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] |
| 540 | bl save_and_update_ptw_el1_sys_regs |
| 541 | ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] |
| 542 | #endif |
| 543 | .endm |
| 544 | |
| 545 | .macro restore_ptw_el1_sys_regs |
| 546 | #if ERRATA_SPECULATIVE_AT |
| 547 | /* ----------------------------------------------------------- |
| 548 | * In case of ERRATA_SPECULATIVE_AT, must follow below order |
| 549 | * to ensure that page table walk is not enabled until |
| 550 | * restoration of all EL1 system registers. TCR_EL1 register |
| 551 | * should be updated at the end which restores previous page |
| 552 | * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB |
| 553 | * ensures that CPU does below steps in order. |
| 554 | * |
| 555 | * 1. Ensure all other system registers are written before |
| 556 | * updating SCTLR_EL1 using ISB. |
| 557 | * 2. Restore SCTLR_EL1 register. |
| 558 | * 3. Ensure SCTLR_EL1 written successfully using ISB. |
| 559 | * 4. Restore TCR_EL1 register. |
| 560 | * ----------------------------------------------------------- |
| 561 | */ |
| 562 | isb |
| 563 | ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1] |
| 564 | msr sctlr_el1, x28 |
| 565 | isb |
| 566 | msr tcr_el1, x29 |
| 567 | #endif |
| 568 | .endm |
| 569 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 570 | #endif /* EL3_COMMON_MACROS_S */ |