Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4e6408c | 2019-01-23 16:23:07 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <drivers/arm/tzc400.h> |
| 11 | #if TRUSTED_BOARD_BOOT |
| 12 | #include <drivers/auth/mbedtls/mbedtls_config.h> |
| 13 | #endif |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 14 | #include <plat/arm/board/common/board_css_def.h> |
| 15 | #include <plat/arm/board/common/v2m_def.h> |
| 16 | #include <plat/arm/common/arm_def.h> |
| 17 | #include <plat/arm/css/common/css_def.h> |
| 18 | #include <plat/arm/soc/common/soc_css_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 19 | #include <plat/common/common_def.h> |
| 20 | |
Sandrine Bailleux | 1fe4336 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 21 | #include "../juno_def.h" |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 22 | |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 23 | /* Required platform porting definitions */ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 24 | /* Juno supports system power domain */ |
| 25 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
| 26 | #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 27 | JUNO_CLUSTER_COUNT + \ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 28 | PLATFORM_CORE_COUNT) |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 29 | #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ |
| 30 | JUNO_CLUSTER1_CORE_COUNT) |
| 31 | |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 32 | /* Cryptocell HW Base address */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 33 | #define PLAT_CRYPTOCELL_BASE UL(0x60050000) |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 34 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 35 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 36 | * Other platform porting definitions are provided by included headers |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 37 | */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 38 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 39 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 40 | * Required ARM standard platform porting definitions |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 41 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 42 | #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 43 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 44 | #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 45 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 46 | /* Use the bypass address */ |
Sathees Balya | 6f07a60 | 2018-11-02 14:56:06 +0000 | [diff] [blame] | 47 | #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ |
| 48 | BL1_ROM_BYPASS_OFFSET) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 49 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 50 | #define NSRAM_BASE UL(0x2e000000) |
| 51 | #define NSRAM_SIZE UL(0x00008000) /* 32KB */ |
Chris Kay | 42fbdfc | 2018-05-10 14:27:45 +0100 | [diff] [blame] | 52 | |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 53 | /* virtual address used by dynamic mem_protect for chunk_base */ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 54 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 55 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 56 | /* |
Sathees Balya | 6f07a60 | 2018-11-02 14:56:06 +0000 | [diff] [blame] | 57 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 58 | */ |
| 59 | |
| 60 | #if USE_ROMLIB |
| 61 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) |
| 62 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) |
| 63 | #else |
| 64 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) |
| 65 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) |
| 66 | #endif |
| 67 | |
| 68 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 69 | * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB |
| 70 | * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of |
| 71 | * flash |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 72 | */ |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 73 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 74 | #if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 75 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 76 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 77 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 78 | #endif /* TRUSTED_BOARD_BOOT */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 79 | |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 80 | /* |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 81 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 82 | * plat_arm_mmap array defined for each BL stage. |
| 83 | */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 84 | #ifdef IMAGE_BL1 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 85 | # define PLAT_ARM_MMAP_ENTRIES 7 |
| 86 | # define MAX_XLAT_TABLES 4 |
| 87 | #endif |
| 88 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 89 | #ifdef IMAGE_BL2 |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 90 | #ifdef SPD_opteed |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 91 | # define PLAT_ARM_MMAP_ENTRIES 11 |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 92 | # define MAX_XLAT_TABLES 5 |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 93 | #else |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 94 | # define PLAT_ARM_MMAP_ENTRIES 10 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 95 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 96 | #endif |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 97 | #endif |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 98 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 99 | #ifdef IMAGE_BL2U |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 100 | # define PLAT_ARM_MMAP_ENTRIES 5 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 101 | # define MAX_XLAT_TABLES 3 |
| 102 | #endif |
| 103 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 104 | #ifdef IMAGE_BL31 |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 105 | # define PLAT_ARM_MMAP_ENTRIES 7 |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 106 | # define MAX_XLAT_TABLES 3 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 107 | #endif |
| 108 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 109 | #ifdef IMAGE_BL32 |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 110 | # define PLAT_ARM_MMAP_ENTRIES 6 |
Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 111 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 112 | #endif |
| 113 | |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 114 | /* |
| 115 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 116 | * plus a little space for growth. |
| 117 | */ |
| 118 | #if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 119 | # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 120 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 121 | # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 122 | #endif |
| 123 | |
| 124 | /* |
| 125 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 126 | * little space for growth. |
| 127 | */ |
| 128 | #if TRUSTED_BOARD_BOOT |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 129 | #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 130 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x1F000) |
Amit Daniel Kachhap | 4a8c7f9 | 2018-03-23 11:56:23 +0530 | [diff] [blame] | 131 | #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 132 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 133 | #else |
Sathees Balya | 9095009 | 2018-11-15 14:22:30 +0000 | [diff] [blame] | 134 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 135 | #endif |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 136 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 137 | # define PLAT_ARM_MAX_BL2_SIZE UL(0xF000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 138 | #endif |
| 139 | |
| 140 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 141 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 142 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 143 | * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. |
| 144 | * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 145 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 146 | #define PLAT_ARM_MAX_BL31_SIZE UL(0x3E000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 147 | |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 148 | #if JUNO_AARCH32_EL3_RUNTIME |
| 149 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 150 | * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is |
| 151 | * calculated using the current BL32 PROGBITS debug size plus the sizes of |
| 152 | * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. |
| 153 | * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 154 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 155 | #define PLAT_ARM_MAX_BL32_SIZE UL(0x3E000) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 156 | #endif |
| 157 | |
Soby Mathew | 39f9c16 | 2017-08-22 14:06:19 +0100 | [diff] [blame] | 158 | /* |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 159 | * Size of cacheable stacks |
| 160 | */ |
| 161 | #if defined(IMAGE_BL1) |
| 162 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 163 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 164 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 165 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 166 | # endif |
| 167 | #elif defined(IMAGE_BL2) |
| 168 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 169 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 170 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 171 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 172 | # endif |
| 173 | #elif defined(IMAGE_BL2U) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 174 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 175 | #elif defined(IMAGE_BL31) |
| 176 | # if PLAT_XLAT_TABLES_DYNAMIC |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 177 | # define PLATFORM_STACK_SIZE UL(0x800) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 178 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 179 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 180 | # endif |
| 181 | #elif defined(IMAGE_BL32) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 182 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 183 | #endif |
| 184 | |
| 185 | /* |
Soby Mathew | 39f9c16 | 2017-08-22 14:06:19 +0100 | [diff] [blame] | 186 | * Since free SRAM space is scant, enable the ASSERTION message size |
| 187 | * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). |
| 188 | */ |
| 189 | #define PLAT_LOG_LEVEL_ASSERT 40 |
| 190 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 191 | /* CCI related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 192 | #define PLAT_ARM_CCI_BASE UL(0x2c090000) |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 193 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 194 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 195 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 196 | /* System timer related constants */ |
Antonio Nino Diaz | 6971f00 | 2018-11-06 13:14:21 +0000 | [diff] [blame] | 197 | #define PLAT_ARM_NSTIMER_FRAME_ID U(1) |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 198 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 199 | /* TZC related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 200 | #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 201 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 202 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ |
| 203 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ |
| 204 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ |
| 205 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ |
| 206 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ |
| 207 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ |
| 208 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ |
| 209 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ |
| 210 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ |
| 211 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 212 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 213 | /* |
| 214 | * Required ARM CSS based platform porting definitions |
| 215 | */ |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 216 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 217 | /* GIC related constants (no GICR in GIC-400) */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 218 | #define PLAT_ARM_GICD_BASE UL(0x2c010000) |
| 219 | #define PLAT_ARM_GICC_BASE UL(0x2c02f000) |
| 220 | #define PLAT_ARM_GICH_BASE UL(0x2c04f000) |
| 221 | #define PLAT_ARM_GICV_BASE UL(0x2c06f000) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 222 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 223 | /* MHU related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 224 | #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) |
Masahisa Kojima | 0d31688 | 2019-03-07 11:23:42 +0900 | [diff] [blame] | 225 | #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 226 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 227 | /* |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 228 | * Base address of the first memory region used for communication between AP |
| 229 | * and SCP. Used by the BOM and SCPI protocols. |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 230 | */ |
| 231 | #if !CSS_USE_SCMI_SDS_DRIVER |
| 232 | /* |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 233 | * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which |
| 234 | * means the SCP/AP configuration data gets overwritten when the AP initiates |
| 235 | * communication with the SCP. The configuration data is expected to be a |
| 236 | * 32-bit word on all CSS platforms. On Juno, part of this configuration is |
| 237 | * which CPU is the primary, according to the shift and mask definitions below. |
| 238 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 239 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 240 | #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 |
| 241 | #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 242 | #endif |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 243 | |
| 244 | /* |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 245 | * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current |
| 246 | * SCP_BL2 size plus a little space for growth. |
| 247 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 248 | #define PLAT_CSS_MAX_SCP_BL2_SIZE UL(0x14000) |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 249 | |
| 250 | /* |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 251 | * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current |
| 252 | * SCP_BL2U size plus a little space for growth. |
| 253 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 254 | #define PLAT_CSS_MAX_SCP_BL2U_SIZE UL(0x14000) |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 255 | |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 256 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 257 | CSS_G1S_IRQ_PROPS(grp), \ |
| 258 | ARM_G1S_IRQ_PROPS(grp), \ |
| 259 | INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 260 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 261 | INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 262 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 263 | INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 264 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 265 | INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 266 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 267 | INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 268 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 269 | INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 270 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 271 | INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 272 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 273 | INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 274 | (grp), GIC_INTR_CFG_LEVEL) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 275 | |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 276 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 277 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 278 | /* |
| 279 | * Required ARM CSS SoC based platform porting definitions |
| 280 | */ |
| 281 | |
| 282 | /* CSS SoC NIC-400 Global Programmers View (GPV) */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 283 | #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 284 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 285 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS |
| 286 | #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS |
| 287 | |
Chandni Cherukuri | 0fdcbc0 | 2018-10-16 15:19:54 +0530 | [diff] [blame] | 288 | /* System power domain level */ |
| 289 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 |
| 290 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 291 | /* |
| 292 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 293 | */ |
| 294 | #ifdef AARCH64 |
| 295 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 296 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
| 297 | #else |
| 298 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 299 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 300 | #endif |
| 301 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 302 | #endif /* PLATFORM_DEF_H */ |