| Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PLATFORM_DEF_H__ |
| 32 | #define __PLATFORM_DEF_H__ |
| 33 | |
| 34 | #include <arch.h> |
| 35 | |
| 36 | /******************************************************************************* |
| 37 | * Platform binary types for linking |
| 38 | ******************************************************************************/ |
| 39 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 40 | #define PLATFORM_LINKER_ARCH aarch64 |
| 41 | |
| 42 | /******************************************************************************* |
| 43 | * Generic platform constants |
| 44 | ******************************************************************************/ |
| 45 | |
| 46 | /* Size of cacheable stacks */ |
| 47 | #define PLATFORM_STACK_SIZE 0x800 |
| 48 | |
| 49 | #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" |
| 50 | |
| 51 | /* Trusted Boot Firmware BL2 */ |
| 52 | #define BL2_IMAGE_NAME "bl2.bin" |
| 53 | |
| 54 | /* EL3 Runtime Firmware BL3-1 */ |
| 55 | #define BL31_IMAGE_NAME "bl31.bin" |
| 56 | |
| 57 | /* SCP Firmware BL3-0 */ |
| 58 | #define BL30_IMAGE_NAME "bl30.bin" |
| 59 | |
| 60 | /* Secure Payload BL3-2 (Trusted OS) */ |
| 61 | #define BL32_IMAGE_NAME "bl32.bin" |
| 62 | |
| 63 | /* Non-Trusted Firmware BL3-3 */ |
| 64 | #define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ |
| 65 | |
| 66 | /* Firmware Image Package */ |
| 67 | #define FIP_IMAGE_NAME "fip.bin" |
| 68 | |
| 69 | #define PLATFORM_CACHE_LINE_SIZE 64 |
| 70 | #define PLATFORM_CLUSTER_COUNT 2 |
| 71 | #define PLATFORM_CORE_COUNT 6 |
| 72 | #define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ |
| 73 | PLATFORM_CORE_COUNT) |
| 74 | #define MAX_IO_DEVICES 3 |
| 75 | #define MAX_IO_HANDLES 4 |
| 76 | |
| 77 | /******************************************************************************* |
| 78 | * Platform memory map related constants |
| 79 | ******************************************************************************/ |
| 80 | #define FLASH_BASE 0x08000000 |
| 81 | #define FLASH_SIZE 0x04000000 |
| 82 | |
| 83 | /* Bypass offset from start of NOR flash */ |
| 84 | #define BL1_ROM_BYPASS_OFFSET 0x03EC0000 |
| 85 | |
| 86 | #ifndef TZROM_BASE |
| 87 | /* Use the bypass address */ |
| 88 | #define TZROM_BASE FLASH_BASE + BL1_ROM_BYPASS_OFFSET |
| 89 | #endif |
| 90 | #define TZROM_SIZE 0x00010000 |
| 91 | |
| 92 | #define TZRAM_BASE 0x04001000 |
| 93 | #define TZRAM_SIZE 0x0003F000 |
| 94 | |
| 95 | /******************************************************************************* |
| 96 | * BL1 specific defines. |
| 97 | * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base |
| 98 | * addresses. |
| 99 | ******************************************************************************/ |
| 100 | #define BL1_RO_BASE TZROM_BASE |
| 101 | #define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE) |
| 102 | #define BL1_RW_BASE TZRAM_BASE |
| 103 | #define BL1_RW_LIMIT BL31_BASE |
| 104 | |
| 105 | /******************************************************************************* |
| 106 | * BL2 specific defines. |
| 107 | ******************************************************************************/ |
| 108 | #define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xd000) |
| 109 | #define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE) |
| 110 | |
| 111 | /******************************************************************************* |
| 112 | * Load address of BL3-0 in the Juno port |
| 113 | * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the |
| 114 | * SCP, it is discarded and BL3-1 is loaded over the top. |
| 115 | ******************************************************************************/ |
| 116 | #define BL30_BASE BL31_BASE |
| 117 | |
| 118 | /******************************************************************************* |
| 119 | * BL3-1 specific defines. |
| 120 | ******************************************************************************/ |
| 121 | #define BL31_BASE (TZRAM_BASE + 0x8000) |
| 122 | #define BL31_LIMIT BL32_BASE |
| 123 | |
| 124 | /******************************************************************************* |
| 125 | * BL3-2 specific defines. |
| 126 | ******************************************************************************/ |
| 127 | #define TSP_SEC_MEM_BASE TZRAM_BASE |
| 128 | #define TSP_SEC_MEM_SIZE TZRAM_SIZE |
| 129 | #define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1d000) |
| 130 | #define BL32_LIMIT BL2_BASE |
| 131 | |
| 132 | /******************************************************************************* |
| 133 | * Load address of BL3-3 in the Juno port |
| 134 | ******************************************************************************/ |
| 135 | #define NS_IMAGE_OFFSET 0xE0000000 |
| 136 | |
| 137 | /******************************************************************************* |
| 138 | * Platform specific page table and MMU setup constants |
| 139 | ******************************************************************************/ |
| 140 | #define ADDR_SPACE_SIZE (1ull << 32) |
| 141 | #define MAX_XLAT_TABLES 2 |
| 142 | #define MAX_MMAP_REGIONS 16 |
| 143 | |
| 144 | /******************************************************************************* |
| 145 | * ID of the secure physical generic timer interrupt. |
| 146 | ******************************************************************************/ |
| 147 | #define IRQ_SEC_PHY_TIMER 29 |
| 148 | |
| 149 | /******************************************************************************* |
| 150 | * Declarations and constants to access the mailboxes safely. Each mailbox is |
| 151 | * aligned on the biggest cache line size in the platform. This is known only |
| 152 | * to the platform as it might have a combination of integrated and external |
| 153 | * caches. Such alignment ensures that two maiboxes do not sit on the same cache |
| 154 | * line at any cache level. They could belong to different cpus/clusters & |
| 155 | * get written while being protected by different locks causing corruption of |
| 156 | * a valid mailbox address. |
| 157 | ******************************************************************************/ |
| 158 | #define CACHE_WRITEBACK_SHIFT 6 |
| 159 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 160 | |
| 161 | #endif /* __PLATFORM_DEF_H__ */ |