Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __TEGRA_DEF_H__ |
| 32 | #define __TEGRA_DEF_H__ |
| 33 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 34 | /******************************************************************************* |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 35 | * These values are used by the PSCI implementation during the `CPU_SUSPEND` |
| 36 | * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' |
| 37 | * parameter. |
| 38 | ******************************************************************************/ |
| 39 | #define PSTATE_ID_CORE_IDLE 6 |
| 40 | #define PSTATE_ID_CORE_POWERDN 7 |
| 41 | #define PSTATE_ID_SOC_POWERDN 2 |
| 42 | |
| 43 | /******************************************************************************* |
| 44 | * Platform power states (used by PSCI framework) |
| 45 | * |
| 46 | * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID |
| 47 | * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 48 | ******************************************************************************/ |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 49 | #define PLAT_MAX_RET_STATE 1 |
| 50 | #define PLAT_MAX_OFF_STATE 8 |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 51 | |
| 52 | /******************************************************************************* |
| 53 | * Implementation defined ACTLR_EL3 bit definitions |
| 54 | ******************************************************************************/ |
| 55 | #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) |
| 56 | #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) |
| 57 | #define ACTLR_EL3_L2CTLR_BIT (1 << 4) |
| 58 | #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) |
| 59 | #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) |
| 60 | #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ |
| 61 | ACTLR_EL3_L2ECTLR_BIT | \ |
| 62 | ACTLR_EL3_L2CTLR_BIT | \ |
| 63 | ACTLR_EL3_CPUECTLR_BIT | \ |
| 64 | ACTLR_EL3_CPUACTLR_BIT) |
| 65 | |
| 66 | /******************************************************************************* |
Varun Wadekar | cad7b08 | 2015-12-28 18:12:59 -0800 | [diff] [blame] | 67 | * Secure IRQ definitions |
| 68 | ******************************************************************************/ |
| 69 | #define TEGRA186_TOP_WDT_IRQ 49 |
| 70 | #define TEGRA186_AON_WDT_IRQ 50 |
| 71 | |
| 72 | #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ |
| 73 | |
| 74 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 75 | * Tegra Miscellanous register constants |
| 76 | ******************************************************************************/ |
| 77 | #define TEGRA_MISC_BASE 0x00100000 |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 78 | #define HARDWARE_REVISION_OFFSET 0x4 |
Varun Wadekar | e2bc7f2 | 2016-04-02 15:41:20 -0700 | [diff] [blame] | 79 | |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 80 | #define MISCREG_PFCFG 0x200C |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 81 | |
| 82 | /******************************************************************************* |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 83 | * Tegra TSA Controller constants |
| 84 | ******************************************************************************/ |
| 85 | #define TEGRA_TSA_BASE 0x02400000 |
| 86 | |
| 87 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 88 | * Tegra Memory Controller constants |
| 89 | ******************************************************************************/ |
| 90 | #define TEGRA_MC_STREAMID_BASE 0x02C00000 |
| 91 | #define TEGRA_MC_BASE 0x02C10000 |
| 92 | |
| 93 | /******************************************************************************* |
| 94 | * Tegra UART Controller constants |
| 95 | ******************************************************************************/ |
| 96 | #define TEGRA_UARTA_BASE 0x03100000 |
| 97 | #define TEGRA_UARTB_BASE 0x03110000 |
| 98 | #define TEGRA_UARTC_BASE 0x0C280000 |
| 99 | #define TEGRA_UARTD_BASE 0x03130000 |
| 100 | #define TEGRA_UARTE_BASE 0x03140000 |
| 101 | #define TEGRA_UARTF_BASE 0x03150000 |
| 102 | #define TEGRA_UARTG_BASE 0x0C290000 |
| 103 | |
| 104 | /******************************************************************************* |
Varun Wadekar | 4debe05 | 2016-05-18 13:39:16 -0700 | [diff] [blame] | 105 | * Tegra Fuse Controller related constants |
| 106 | ******************************************************************************/ |
| 107 | #define TEGRA_FUSE_BASE 0x03820000 |
| 108 | #define OPT_SUBREVISION 0x248 |
| 109 | #define SUBREVISION_MASK 0xFF |
| 110 | |
| 111 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 112 | * GICv2 & interrupt handling related constants |
| 113 | ******************************************************************************/ |
| 114 | #define TEGRA_GICD_BASE 0x03881000 |
| 115 | #define TEGRA_GICC_BASE 0x03882000 |
| 116 | |
| 117 | /******************************************************************************* |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 118 | * Security Engine related constants |
| 119 | ******************************************************************************/ |
| 120 | #define TEGRA_SE0_BASE 0x03AC0000 |
| 121 | #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C |
| 122 | #define TEGRA_PKA1_BASE 0x03AD0000 |
| 123 | #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 |
| 124 | #define TEGRA_RNG1_BASE 0x03AE0000 |
| 125 | #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 |
| 126 | |
| 127 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 128 | * Tegra Clock and Reset Controller constants |
| 129 | ******************************************************************************/ |
| 130 | #define TEGRA_CAR_RESET_BASE 0x05000000 |
| 131 | |
| 132 | /******************************************************************************* |
| 133 | * Tegra micro-seconds timer constants |
| 134 | ******************************************************************************/ |
| 135 | #define TEGRA_TMRUS_BASE 0x0C2E0000 |
| 136 | |
| 137 | /******************************************************************************* |
| 138 | * Tegra Power Mgmt Controller constants |
| 139 | ******************************************************************************/ |
| 140 | #define TEGRA_PMC_BASE 0x0C360000 |
| 141 | |
| 142 | /******************************************************************************* |
| 143 | * Tegra scratch registers constants |
| 144 | ******************************************************************************/ |
| 145 | #define TEGRA_SCRATCH_BASE 0x0C390000 |
Varun Wadekar | b877615 | 2016-03-03 13:52:52 -0800 | [diff] [blame] | 146 | #define SECURE_SCRATCH_RSV6 0x680 |
| 147 | #define SECURE_SCRATCH_RSV11_LO 0x6A8 |
| 148 | #define SECURE_SCRATCH_RSV11_HI 0x6AC |
Varun Wadekar | 94701ff | 2016-05-23 11:47:34 -0700 | [diff] [blame] | 149 | #define SECURE_SCRATCH_RSV53_LO 0x7F8 |
| 150 | #define SECURE_SCRATCH_RSV53_HI 0x7FC |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 151 | |
| 152 | /******************************************************************************* |
| 153 | * Tegra Memory Mapped Control Register Access Bus constants |
| 154 | ******************************************************************************/ |
| 155 | #define TEGRA_MMCRAB_BASE 0x0E000000 |
| 156 | |
| 157 | /******************************************************************************* |
| 158 | * Tegra SMMU Controller constants |
| 159 | ******************************************************************************/ |
| 160 | #define TEGRA_SMMU_BASE 0x12000000 |
| 161 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 162 | /******************************************************************************* |
| 163 | * Tegra TZRAM constants |
| 164 | ******************************************************************************/ |
| 165 | #define TEGRA_TZRAM_BASE 0x30000000 |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 166 | #define TEGRA_TZRAM_SIZE 0x40000 |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 167 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 168 | #endif /* __TEGRA_DEF_H__ */ |