Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 1 | /* |
Govindraj Raja | 805dc80 | 2023-06-15 12:39:48 -0500 | [diff] [blame] | 2 | * Copyright (c) 2019-2023, Arm Limited. All rights reserved. |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
Jimmy Brisson | 7ec175e | 2020-06-01 16:49:34 -0500 | [diff] [blame] | 10 | #include <cortex_a78.h> |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 17 | #error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 18 | #endif |
| 19 | |
Saurabh Gorecha | b849301 | 2022-04-05 00:11:52 +0530 | [diff] [blame] | 20 | .globl cortex_a78_reset_func |
| 21 | .globl cortex_a78_core_pwr_dwn |
| 22 | |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 23 | #if WORKAROUND_CVE_2022_23960 |
| 24 | wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78 |
| 25 | #endif /* WORKAROUND_CVE_2022_23960 */ |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 26 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 27 | workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305 |
Govindraj Raja | 1087d50 | 2023-06-15 15:23:58 -0500 | [diff] [blame] | 28 | sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 29 | workaround_reset_end cortex_a78, ERRATUM(1688305) |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 30 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 31 | check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0) |
Govindraj Raja | 805dc80 | 2023-06-15 12:39:48 -0500 | [diff] [blame] | 32 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 33 | workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534 |
Govindraj Raja | 1087d50 | 2023-06-15 15:23:58 -0500 | [diff] [blame] | 34 | sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 35 | workaround_reset_end cortex_a78, ERRATUM(1821534) |
Govindraj Raja | 805dc80 | 2023-06-15 12:39:48 -0500 | [diff] [blame] | 36 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 37 | check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0) |
Govindraj Raja | 805dc80 | 2023-06-15 12:39:48 -0500 | [diff] [blame] | 38 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 39 | workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498 |
Govindraj Raja | 1087d50 | 2023-06-15 15:23:58 -0500 | [diff] [blame] | 40 | sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 41 | workaround_reset_end cortex_a78, ERRATUM(1941498) |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 42 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 43 | check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1) |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 44 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 45 | workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500 |
johpow01 | 85ea43d | 2020-10-07 15:08:01 -0500 | [diff] [blame] | 46 | msr S3_6_c15_c8_0, xzr |
| 47 | ldr x0, =0x10E3900002 |
| 48 | msr S3_6_c15_c8_2, x0 |
| 49 | ldr x0, =0x10FFF00083 |
| 50 | msr S3_6_c15_c8_3, x0 |
| 51 | ldr x0, =0x2001003FF |
| 52 | msr S3_6_c15_c8_1, x0 |
| 53 | |
| 54 | mov x0, #1 |
| 55 | msr S3_6_c15_c8_0, x0 |
| 56 | ldr x0, =0x10E3800082 |
| 57 | msr S3_6_c15_c8_2, x0 |
| 58 | ldr x0, =0x10FFF00083 |
| 59 | msr S3_6_c15_c8_3, x0 |
| 60 | ldr x0, =0x2001003FF |
| 61 | msr S3_6_c15_c8_1, x0 |
| 62 | |
| 63 | mov x0, #2 |
| 64 | msr S3_6_c15_c8_0, x0 |
| 65 | ldr x0, =0x10E3800200 |
| 66 | msr S3_6_c15_c8_2, x0 |
| 67 | ldr x0, =0x10FFF003E0 |
| 68 | msr S3_6_c15_c8_3, x0 |
| 69 | ldr x0, =0x2001003FF |
| 70 | msr S3_6_c15_c8_1, x0 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 71 | workaround_reset_end cortex_a78, ERRATUM(1951500) |
johpow01 | 85ea43d | 2020-10-07 15:08:01 -0500 | [diff] [blame] | 72 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 73 | check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1) |
nayanpatel-arm | 80bf7a5 | 2021-08-11 13:33:00 -0700 | [diff] [blame] | 74 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 75 | workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683 |
nayanpatel-arm | 80bf7a5 | 2021-08-11 13:33:00 -0700 | [diff] [blame] | 76 | ldr x0,=0x5 |
| 77 | msr S3_6_c15_c8_0,x0 |
| 78 | ldr x0,=0xEEE10A10 |
| 79 | msr S3_6_c15_c8_2,x0 |
| 80 | ldr x0,=0xFFEF0FFF |
| 81 | msr S3_6_c15_c8_3,x0 |
| 82 | ldr x0,=0x0010F000 |
| 83 | msr S3_6_c15_c8_4,x0 |
| 84 | ldr x0,=0x0010F000 |
| 85 | msr S3_6_c15_c8_5,x0 |
| 86 | ldr x0,=0x40000080023ff |
| 87 | msr S3_6_c15_c8_1,x0 |
| 88 | ldr x0,=0x6 |
| 89 | msr S3_6_c15_c8_0,x0 |
| 90 | ldr x0,=0xEE640F34 |
| 91 | msr S3_6_c15_c8_2,x0 |
| 92 | ldr x0,=0xFFEF0FFF |
| 93 | msr S3_6_c15_c8_3,x0 |
| 94 | ldr x0,=0x40000080023ff |
| 95 | msr S3_6_c15_c8_1,x0 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 96 | workaround_reset_end cortex_a78, ERRATUM(1952683) |
nayanpatel-arm | 80bf7a5 | 2021-08-11 13:33:00 -0700 | [diff] [blame] | 97 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 98 | check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0) |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 99 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 100 | workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060 |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 101 | /* Apply the workaround. */ |
| 102 | mrs x1, CORTEX_A78_CPUECTLR_EL1 |
| 103 | mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV |
| 104 | bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH |
| 105 | msr CORTEX_A78_CPUECTLR_EL1, x1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 106 | workaround_reset_end cortex_a78, ERRATUM(2132060) |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 107 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 108 | check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2) |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 109 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 110 | workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635 |
johpow01 | 45c1724 | 2021-09-02 17:53:30 -0500 | [diff] [blame] | 111 | ldr x0, =0x5 |
| 112 | msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ |
| 113 | ldr x0, =0x10F600E000 |
| 114 | msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ |
| 115 | ldr x0, =0x10FF80E000 |
| 116 | msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ |
| 117 | ldr x0, =0x80000000003FF |
| 118 | msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 119 | workaround_reset_end cortex_a78, ERRATUM(2242635) |
johpow01 | 45c1724 | 2021-09-02 17:53:30 -0500 | [diff] [blame] | 120 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 121 | check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2) |
johpow01 | 45c1724 | 2021-09-02 17:53:30 -0500 | [diff] [blame] | 122 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 123 | workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745 |
Govindraj Raja | 1087d50 | 2023-06-15 15:23:58 -0500 | [diff] [blame] | 124 | sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0) |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 125 | workaround_reset_end cortex_a78, ERRATUM(2376745) |
John Powell | 12bc0de | 2022-05-03 15:22:57 -0500 | [diff] [blame] | 126 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 127 | check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2) |
John Powell | a93b7e5 | 2022-05-03 15:52:11 -0500 | [diff] [blame] | 128 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 129 | workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406 |
Govindraj Raja | 1087d50 | 2023-06-15 15:23:58 -0500 | [diff] [blame] | 130 | sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40) |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 131 | workaround_reset_end cortex_a78, ERRATUM(2395406) |
John Powell | a93b7e5 | 2022-05-03 15:52:11 -0500 | [diff] [blame] | 132 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 133 | check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2) |
John Powell | a93b7e5 | 2022-05-03 15:52:11 -0500 | [diff] [blame] | 134 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 135 | workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426 |
Bipin Ravi | 33100ef | 2023-02-28 14:51:28 -0600 | [diff] [blame] | 136 | /* Apply the workaround */ |
| 137 | mrs x1, CORTEX_A78_ACTLR5_EL1 |
| 138 | bic x1, x1, #BIT(56) |
| 139 | orr x1, x1, #BIT(55) |
| 140 | msr CORTEX_A78_ACTLR5_EL1, x1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 141 | workaround_reset_end cortex_a78, ERRATUM(2742426) |
Bipin Ravi | 33100ef | 2023-02-28 14:51:28 -0600 | [diff] [blame] | 142 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 143 | check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2) |
Bipin Ravi | 33100ef | 2023-02-28 14:51:28 -0600 | [diff] [blame] | 144 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 145 | workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 |
Bipin Ravi | 8f78e0d | 2022-12-15 14:48:21 -0600 | [diff] [blame] | 146 | /* dsb before isb of power down sequence */ |
| 147 | dsb sy |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 148 | workaround_runtime_end cortex_a78, ERRATUM(2772019) |
Bipin Ravi | 8f78e0d | 2022-12-15 14:48:21 -0600 | [diff] [blame] | 149 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 150 | check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2) |
Bipin Ravi | 8f78e0d | 2022-12-15 14:48:21 -0600 | [diff] [blame] | 151 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 152 | workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479 |
Govindraj Raja | 1087d50 | 2023-06-15 15:23:58 -0500 | [diff] [blame] | 153 | sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47) |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 154 | workaround_reset_end cortex_a78, ERRATUM(2779479) |
Sona Mathew | f13c1a9 | 2023-01-11 12:55:30 -0600 | [diff] [blame] | 155 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 156 | check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2) |
Sona Mathew | f13c1a9 | 2023-01-11 12:55:30 -0600 | [diff] [blame] | 157 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 158 | workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 159 | #if IMAGE_BL31 |
| 160 | /* |
| 161 | * The Cortex-X1 generic vectors are overridden to apply errata |
| 162 | * mitigation on exception entry from lower ELs. |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 163 | */ |
Govindraj Raja | 1087d50 | 2023-06-15 15:23:58 -0500 | [diff] [blame] | 164 | override_vector_table wa_cve_vbar_cortex_a78 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 165 | #endif /* IMAGE_BL31 */ |
| 166 | workaround_reset_end cortex_a78, CVE(2022, 23960) |
Bipin Ravi | 33100ef | 2023-02-28 14:51:28 -0600 | [diff] [blame] | 167 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 168 | check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Sona Mathew | f13c1a9 | 2023-01-11 12:55:30 -0600 | [diff] [blame] | 169 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 170 | cpu_reset_func_start cortex_a78 |
Andre Przywara | 0b7f1b0 | 2023-03-21 13:53:19 +0000 | [diff] [blame] | 171 | #if ENABLE_FEAT_AMU |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 172 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
Govindraj Raja | 1087d50 | 2023-06-15 15:23:58 -0500 | [diff] [blame] | 173 | sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 174 | |
| 175 | /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ |
Govindraj Raja | 1087d50 | 2023-06-15 15:23:58 -0500 | [diff] [blame] | 176 | sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 177 | |
| 178 | /* Enable group0 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 179 | mov x0, #CORTEX_A78_AMU_GROUP0_MASK |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 180 | msr CPUAMCNTENSET0_EL0, x0 |
| 181 | |
| 182 | /* Enable group1 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 183 | mov x0, #CORTEX_A78_AMU_GROUP1_MASK |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 184 | msr CPUAMCNTENSET1_EL0, x0 |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 185 | #endif |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 186 | cpu_reset_func_end cortex_a78 |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 187 | |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 188 | /* --------------------------------------------- |
| 189 | * HW will do the cache maintenance while powering down |
| 190 | * --------------------------------------------- |
| 191 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 192 | func cortex_a78_core_pwr_dwn |
Govindraj Raja | 1087d50 | 2023-06-15 15:23:58 -0500 | [diff] [blame] | 193 | sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 194 | |
| 195 | apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 |
| 196 | |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 197 | isb |
| 198 | ret |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 199 | endfunc cortex_a78_core_pwr_dwn |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 200 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame] | 201 | errata_report_shim cortex_a78 |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 202 | |
| 203 | /* --------------------------------------------- |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 204 | * This function provides cortex_a78 specific |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 205 | * register information for crash reporting. |
| 206 | * It needs to return with x6 pointing to |
| 207 | * a list of register names in ascii and |
| 208 | * x8 - x15 having values of registers to be |
| 209 | * reported. |
| 210 | * --------------------------------------------- |
| 211 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 212 | .section .rodata.cortex_a78_regs, "aS" |
| 213 | cortex_a78_regs: /* The ascii list of register names to be reported */ |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 214 | .asciz "cpuectlr_el1", "" |
| 215 | |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 216 | func cortex_a78_cpu_reg_dump |
| 217 | adr x6, cortex_a78_regs |
| 218 | mrs x8, CORTEX_A78_CPUECTLR_EL1 |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 219 | ret |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 220 | endfunc cortex_a78_cpu_reg_dump |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 221 | |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 222 | declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ |
| 223 | cortex_a78_reset_func, \ |
| 224 | cortex_a78_core_pwr_dwn |