Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 1 | /* |
Govindraj Raja | 805dc80 | 2023-06-15 12:39:48 -0500 | [diff] [blame] | 2 | * Copyright (c) 2019-2023, Arm Limited. All rights reserved. |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
Jimmy Brisson | 7ec175e | 2020-06-01 16:49:34 -0500 | [diff] [blame] | 10 | #include <cortex_a78.h> |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 17 | #error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 18 | #endif |
| 19 | |
Saurabh Gorecha | b849301 | 2022-04-05 00:11:52 +0530 | [diff] [blame] | 20 | .globl cortex_a78_reset_func |
| 21 | .globl cortex_a78_core_pwr_dwn |
| 22 | |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 23 | #if WORKAROUND_CVE_2022_23960 |
| 24 | wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78 |
| 25 | #endif /* WORKAROUND_CVE_2022_23960 */ |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 26 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 27 | workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 28 | mrs x1, CORTEX_A78_ACTLR2_EL1 |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 29 | orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 30 | msr CORTEX_A78_ACTLR2_EL1, x1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 31 | workaround_reset_end cortex_a78, ERRATUM(1688305) |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 32 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 33 | check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0) |
Govindraj Raja | 805dc80 | 2023-06-15 12:39:48 -0500 | [diff] [blame] | 34 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 35 | workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534 |
Govindraj Raja | 805dc80 | 2023-06-15 12:39:48 -0500 | [diff] [blame] | 36 | /* Set bit 2 in ACTLR2_EL1 */ |
| 37 | mrs x1, CORTEX_A78_ACTLR2_EL1 |
| 38 | orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2 |
| 39 | msr CORTEX_A78_ACTLR2_EL1, x1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 40 | workaround_reset_end cortex_a78, ERRATUM(1821534) |
Govindraj Raja | 805dc80 | 2023-06-15 12:39:48 -0500 | [diff] [blame] | 41 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 42 | check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0) |
Govindraj Raja | 805dc80 | 2023-06-15 12:39:48 -0500 | [diff] [blame] | 43 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 44 | workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498 |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 45 | /* Set bit 8 in ECTLR_EL1 */ |
| 46 | mrs x1, CORTEX_A78_CPUECTLR_EL1 |
| 47 | orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8 |
| 48 | msr CORTEX_A78_CPUECTLR_EL1, x1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 49 | workaround_reset_end cortex_a78, ERRATUM(1941498) |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 50 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 51 | check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1) |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 52 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 53 | workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500 |
johpow01 | 85ea43d | 2020-10-07 15:08:01 -0500 | [diff] [blame] | 54 | msr S3_6_c15_c8_0, xzr |
| 55 | ldr x0, =0x10E3900002 |
| 56 | msr S3_6_c15_c8_2, x0 |
| 57 | ldr x0, =0x10FFF00083 |
| 58 | msr S3_6_c15_c8_3, x0 |
| 59 | ldr x0, =0x2001003FF |
| 60 | msr S3_6_c15_c8_1, x0 |
| 61 | |
| 62 | mov x0, #1 |
| 63 | msr S3_6_c15_c8_0, x0 |
| 64 | ldr x0, =0x10E3800082 |
| 65 | msr S3_6_c15_c8_2, x0 |
| 66 | ldr x0, =0x10FFF00083 |
| 67 | msr S3_6_c15_c8_3, x0 |
| 68 | ldr x0, =0x2001003FF |
| 69 | msr S3_6_c15_c8_1, x0 |
| 70 | |
| 71 | mov x0, #2 |
| 72 | msr S3_6_c15_c8_0, x0 |
| 73 | ldr x0, =0x10E3800200 |
| 74 | msr S3_6_c15_c8_2, x0 |
| 75 | ldr x0, =0x10FFF003E0 |
| 76 | msr S3_6_c15_c8_3, x0 |
| 77 | ldr x0, =0x2001003FF |
| 78 | msr S3_6_c15_c8_1, x0 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 79 | workaround_reset_end cortex_a78, ERRATUM(1951500) |
johpow01 | 85ea43d | 2020-10-07 15:08:01 -0500 | [diff] [blame] | 80 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 81 | check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1) |
nayanpatel-arm | 80bf7a5 | 2021-08-11 13:33:00 -0700 | [diff] [blame] | 82 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 83 | workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683 |
nayanpatel-arm | 80bf7a5 | 2021-08-11 13:33:00 -0700 | [diff] [blame] | 84 | ldr x0,=0x5 |
| 85 | msr S3_6_c15_c8_0,x0 |
| 86 | ldr x0,=0xEEE10A10 |
| 87 | msr S3_6_c15_c8_2,x0 |
| 88 | ldr x0,=0xFFEF0FFF |
| 89 | msr S3_6_c15_c8_3,x0 |
| 90 | ldr x0,=0x0010F000 |
| 91 | msr S3_6_c15_c8_4,x0 |
| 92 | ldr x0,=0x0010F000 |
| 93 | msr S3_6_c15_c8_5,x0 |
| 94 | ldr x0,=0x40000080023ff |
| 95 | msr S3_6_c15_c8_1,x0 |
| 96 | ldr x0,=0x6 |
| 97 | msr S3_6_c15_c8_0,x0 |
| 98 | ldr x0,=0xEE640F34 |
| 99 | msr S3_6_c15_c8_2,x0 |
| 100 | ldr x0,=0xFFEF0FFF |
| 101 | msr S3_6_c15_c8_3,x0 |
| 102 | ldr x0,=0x40000080023ff |
| 103 | msr S3_6_c15_c8_1,x0 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 104 | workaround_reset_end cortex_a78, ERRATUM(1952683) |
nayanpatel-arm | 80bf7a5 | 2021-08-11 13:33:00 -0700 | [diff] [blame] | 105 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 106 | check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0) |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 107 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 108 | workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060 |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 109 | /* Apply the workaround. */ |
| 110 | mrs x1, CORTEX_A78_CPUECTLR_EL1 |
| 111 | mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV |
| 112 | bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH |
| 113 | msr CORTEX_A78_CPUECTLR_EL1, x1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 114 | workaround_reset_end cortex_a78, ERRATUM(2132060) |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 115 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 116 | check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2) |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 117 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 118 | workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635 |
johpow01 | 45c1724 | 2021-09-02 17:53:30 -0500 | [diff] [blame] | 119 | ldr x0, =0x5 |
| 120 | msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ |
| 121 | ldr x0, =0x10F600E000 |
| 122 | msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ |
| 123 | ldr x0, =0x10FF80E000 |
| 124 | msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ |
| 125 | ldr x0, =0x80000000003FF |
| 126 | msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 127 | workaround_reset_end cortex_a78, ERRATUM(2242635) |
johpow01 | 45c1724 | 2021-09-02 17:53:30 -0500 | [diff] [blame] | 128 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 129 | check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2) |
johpow01 | 45c1724 | 2021-09-02 17:53:30 -0500 | [diff] [blame] | 130 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 131 | workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745 |
John Powell | 12bc0de | 2022-05-03 15:22:57 -0500 | [diff] [blame] | 132 | /* Apply the workaround. */ |
| 133 | mrs x1, CORTEX_A78_ACTLR2_EL1 |
| 134 | orr x1, x1, #BIT(0) |
| 135 | msr CORTEX_A78_ACTLR2_EL1, x1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 136 | workaround_reset_end cortex_a78, ERRATUM(2376745) |
John Powell | 12bc0de | 2022-05-03 15:22:57 -0500 | [diff] [blame] | 137 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 138 | check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2) |
John Powell | a93b7e5 | 2022-05-03 15:52:11 -0500 | [diff] [blame] | 139 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 140 | workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406 |
John Powell | a93b7e5 | 2022-05-03 15:52:11 -0500 | [diff] [blame] | 141 | /* Apply the workaround. */ |
| 142 | mrs x1, CORTEX_A78_ACTLR2_EL1 |
| 143 | orr x1, x1, #BIT(40) |
| 144 | msr CORTEX_A78_ACTLR2_EL1, x1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 145 | workaround_reset_end cortex_a78, ERRATUM(2395406) |
John Powell | a93b7e5 | 2022-05-03 15:52:11 -0500 | [diff] [blame] | 146 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 147 | check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2) |
John Powell | a93b7e5 | 2022-05-03 15:52:11 -0500 | [diff] [blame] | 148 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 149 | workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426 |
Bipin Ravi | 33100ef | 2023-02-28 14:51:28 -0600 | [diff] [blame] | 150 | /* Apply the workaround */ |
| 151 | mrs x1, CORTEX_A78_ACTLR5_EL1 |
| 152 | bic x1, x1, #BIT(56) |
| 153 | orr x1, x1, #BIT(55) |
| 154 | msr CORTEX_A78_ACTLR5_EL1, x1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 155 | workaround_reset_end cortex_a78, ERRATUM(2742426) |
Bipin Ravi | 33100ef | 2023-02-28 14:51:28 -0600 | [diff] [blame] | 156 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 157 | check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2) |
Bipin Ravi | 33100ef | 2023-02-28 14:51:28 -0600 | [diff] [blame] | 158 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 159 | workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 |
Bipin Ravi | 8f78e0d | 2022-12-15 14:48:21 -0600 | [diff] [blame] | 160 | /* dsb before isb of power down sequence */ |
| 161 | dsb sy |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 162 | workaround_runtime_end cortex_a78, ERRATUM(2772019) |
Bipin Ravi | 8f78e0d | 2022-12-15 14:48:21 -0600 | [diff] [blame] | 163 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 164 | check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2) |
Bipin Ravi | 8f78e0d | 2022-12-15 14:48:21 -0600 | [diff] [blame] | 165 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 166 | workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479 |
Sona Mathew | f13c1a9 | 2023-01-11 12:55:30 -0600 | [diff] [blame] | 167 | /* Apply the workaround */ |
| 168 | mrs x1, CORTEX_A78_ACTLR3_EL1 |
| 169 | orr x1, x1, #BIT(47) |
| 170 | msr CORTEX_A78_ACTLR3_EL1, x1 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 171 | workaround_reset_end cortex_a78, ERRATUM(2779479) |
Sona Mathew | f13c1a9 | 2023-01-11 12:55:30 -0600 | [diff] [blame] | 172 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 173 | check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2) |
Sona Mathew | f13c1a9 | 2023-01-11 12:55:30 -0600 | [diff] [blame] | 174 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 175 | workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 176 | #if IMAGE_BL31 |
| 177 | /* |
| 178 | * The Cortex-X1 generic vectors are overridden to apply errata |
| 179 | * mitigation on exception entry from lower ELs. |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 180 | */ |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 181 | adr x0, wa_cve_vbar_cortex_a78 |
| 182 | msr vbar_el3, x0 |
| 183 | #endif /* IMAGE_BL31 */ |
| 184 | workaround_reset_end cortex_a78, CVE(2022, 23960) |
Bipin Ravi | 33100ef | 2023-02-28 14:51:28 -0600 | [diff] [blame] | 185 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 186 | check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Sona Mathew | f13c1a9 | 2023-01-11 12:55:30 -0600 | [diff] [blame] | 187 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 188 | cpu_reset_func_start cortex_a78 |
Andre Przywara | 0b7f1b0 | 2023-03-21 13:53:19 +0000 | [diff] [blame] | 189 | #if ENABLE_FEAT_AMU |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 190 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 191 | mrs x0, actlr_el3 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 192 | bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 193 | msr actlr_el3, x0 |
| 194 | |
| 195 | /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ |
| 196 | mrs x0, actlr_el2 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 197 | bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 198 | msr actlr_el2, x0 |
| 199 | |
| 200 | /* Enable group0 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 201 | mov x0, #CORTEX_A78_AMU_GROUP0_MASK |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 202 | msr CPUAMCNTENSET0_EL0, x0 |
| 203 | |
| 204 | /* Enable group1 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 205 | mov x0, #CORTEX_A78_AMU_GROUP1_MASK |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 206 | msr CPUAMCNTENSET1_EL0, x0 |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 207 | #endif |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 208 | cpu_reset_func_end cortex_a78 |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 209 | |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 210 | /* --------------------------------------------- |
| 211 | * HW will do the cache maintenance while powering down |
| 212 | * --------------------------------------------- |
| 213 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 214 | func cortex_a78_core_pwr_dwn |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 215 | /* --------------------------------------------- |
| 216 | * Enable CPU power down bit in power control register |
| 217 | * --------------------------------------------- |
| 218 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 219 | mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 |
| 220 | orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT |
| 221 | msr CORTEX_A78_CPUPWRCTLR_EL1, x0 |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 222 | |
| 223 | apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 |
| 224 | |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 225 | isb |
| 226 | ret |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 227 | endfunc cortex_a78_core_pwr_dwn |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 228 | |
Govindraj Raja | 3f957e7 | 2023-06-15 15:17:38 -0500 | [diff] [blame^] | 229 | errata_report_shim cortex_a78 |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 230 | |
| 231 | /* --------------------------------------------- |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 232 | * This function provides cortex_a78 specific |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 233 | * register information for crash reporting. |
| 234 | * It needs to return with x6 pointing to |
| 235 | * a list of register names in ascii and |
| 236 | * x8 - x15 having values of registers to be |
| 237 | * reported. |
| 238 | * --------------------------------------------- |
| 239 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 240 | .section .rodata.cortex_a78_regs, "aS" |
| 241 | cortex_a78_regs: /* The ascii list of register names to be reported */ |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 242 | .asciz "cpuectlr_el1", "" |
| 243 | |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 244 | func cortex_a78_cpu_reg_dump |
| 245 | adr x6, cortex_a78_regs |
| 246 | mrs x8, CORTEX_A78_CPUECTLR_EL1 |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 247 | ret |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 248 | endfunc cortex_a78_cpu_reg_dump |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 249 | |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 250 | declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ |
| 251 | cortex_a78_reset_func, \ |
| 252 | cortex_a78_core_pwr_dwn |