Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 31 | #include <asm_macros.S> |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 32 | #include <assert_macros.S> |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 33 | #include <bl_common.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 34 | #include <cortex_a57.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 35 | #include <cpu_macros.S> |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 36 | #include <debug.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 37 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 38 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 39 | /* --------------------------------------------- |
| 40 | * Disable L1 data cache and unified L2 cache |
| 41 | * --------------------------------------------- |
| 42 | */ |
| 43 | func cortex_a57_disable_dcache |
| 44 | mrs x1, sctlr_el3 |
| 45 | bic x1, x1, #SCTLR_C_BIT |
| 46 | msr sctlr_el3, x1 |
| 47 | isb |
| 48 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 49 | endfunc cortex_a57_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 50 | |
| 51 | /* --------------------------------------------- |
| 52 | * Disable all types of L2 prefetches. |
| 53 | * --------------------------------------------- |
| 54 | */ |
| 55 | func cortex_a57_disable_l2_prefetch |
| 56 | mrs x0, CPUECTLR_EL1 |
| 57 | orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 58 | mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK |
| 59 | orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK |
| 60 | bic x0, x0, x1 |
| 61 | msr CPUECTLR_EL1, x0 |
| 62 | isb |
Soby Mathew | 1604fa0 | 2014-09-22 12:15:26 +0100 | [diff] [blame] | 63 | dsb ish |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 64 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 65 | endfunc cortex_a57_disable_l2_prefetch |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 66 | |
| 67 | /* --------------------------------------------- |
| 68 | * Disable intra-cluster coherency |
| 69 | * --------------------------------------------- |
| 70 | */ |
| 71 | func cortex_a57_disable_smp |
| 72 | mrs x0, CPUECTLR_EL1 |
| 73 | bic x0, x0, #CPUECTLR_SMP_BIT |
| 74 | msr CPUECTLR_EL1, x0 |
| 75 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 76 | endfunc cortex_a57_disable_smp |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 77 | |
| 78 | /* --------------------------------------------- |
| 79 | * Disable debug interfaces |
| 80 | * --------------------------------------------- |
| 81 | */ |
| 82 | func cortex_a57_disable_ext_debug |
| 83 | mov x0, #1 |
| 84 | msr osdlr_el1, x0 |
| 85 | isb |
| 86 | dsb sy |
| 87 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 88 | endfunc cortex_a57_disable_ext_debug |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 89 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 90 | /* -------------------------------------------------- |
| 91 | * Errata Workaround for Cortex A57 Errata #806969. |
| 92 | * This applies only to revision r0p0 of Cortex A57. |
| 93 | * Inputs: |
| 94 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 95 | * Shall clobber: x0-x17 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 96 | * -------------------------------------------------- |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 97 | */ |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 98 | func errata_a57_806969_wa |
| 99 | /* |
| 100 | * Compare x0 against revision r0p0 |
| 101 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 102 | mov x17, x30 |
| 103 | bl check_errata_806969 |
| 104 | cbz x0, 1f |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 105 | mrs x1, CPUACTLR_EL1 |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 106 | orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 107 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 108 | 1: |
| 109 | ret x17 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 110 | endfunc errata_a57_806969_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 111 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 112 | func check_errata_806969 |
| 113 | mov x1, #0x00 |
| 114 | b cpu_rev_var_ls |
| 115 | endfunc check_errata_806969 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 116 | |
| 117 | /* --------------------------------------------------- |
| 118 | * Errata Workaround for Cortex A57 Errata #813420. |
| 119 | * This applies only to revision r0p0 of Cortex A57. |
| 120 | * Inputs: |
| 121 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 122 | * Shall clobber: x0-x17 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 123 | * --------------------------------------------------- |
| 124 | */ |
| 125 | func errata_a57_813420_wa |
| 126 | /* |
| 127 | * Compare x0 against revision r0p0 |
| 128 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 129 | mov x17, x30 |
| 130 | bl check_errata_813420 |
| 131 | cbz x0, 1f |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 132 | mrs x1, CPUACTLR_EL1 |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 133 | orr x1, x1, #CPUACTLR_DCC_AS_DCCI |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 134 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 135 | 1: |
| 136 | ret x17 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 137 | endfunc errata_a57_813420_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 138 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 139 | func check_errata_813420 |
| 140 | mov x1, #0x00 |
| 141 | b cpu_rev_var_ls |
| 142 | endfunc check_errata_813420 |
| 143 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 144 | /* -------------------------------------------------------------------- |
| 145 | * Disable the over-read from the LDNP instruction. |
| 146 | * |
| 147 | * This applies to all revisions <= r1p2. The performance degradation |
| 148 | * observed with LDNP/STNP has been fixed on r1p3 and onwards. |
| 149 | * |
| 150 | * Inputs: |
| 151 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 152 | * Shall clobber: x0-x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 153 | * --------------------------------------------------------------------- |
| 154 | */ |
| 155 | func a57_disable_ldnp_overread |
| 156 | /* |
| 157 | * Compare x0 against revision r1p2 |
| 158 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 159 | mov x17, x30 |
| 160 | bl check_errata_disable_ldnp_overread |
| 161 | cbz x0, 1f |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 162 | mrs x1, CPUACTLR_EL1 |
| 163 | orr x1, x1, #CPUACTLR_DIS_OVERREAD |
| 164 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 165 | 1: |
| 166 | ret x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 167 | endfunc a57_disable_ldnp_overread |
| 168 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 169 | func check_errata_disable_ldnp_overread |
| 170 | mov x1, #0x12 |
| 171 | b cpu_rev_var_ls |
| 172 | endfunc check_errata_disable_ldnp_overread |
| 173 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 174 | /* --------------------------------------------------- |
| 175 | * Errata Workaround for Cortex A57 Errata #826974. |
| 176 | * This applies only to revision <= r1p1 of Cortex A57. |
| 177 | * Inputs: |
| 178 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 179 | * Shall clobber: x0-x17 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 180 | * --------------------------------------------------- |
| 181 | */ |
| 182 | func errata_a57_826974_wa |
| 183 | /* |
| 184 | * Compare x0 against revision r1p1 |
| 185 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 186 | mov x17, x30 |
| 187 | bl check_errata_826974 |
| 188 | cbz x0, 1f |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 189 | mrs x1, CPUACTLR_EL1 |
| 190 | orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB |
| 191 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 192 | 1: |
| 193 | ret x17 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 194 | endfunc errata_a57_826974_wa |
| 195 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 196 | func check_errata_826974 |
| 197 | mov x1, #0x11 |
| 198 | b cpu_rev_var_ls |
| 199 | endfunc check_errata_826974 |
| 200 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 201 | /* --------------------------------------------------- |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 202 | * Errata Workaround for Cortex A57 Errata #826977. |
| 203 | * This applies only to revision <= r1p1 of Cortex A57. |
| 204 | * Inputs: |
| 205 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 206 | * Shall clobber: x0-x17 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 207 | * --------------------------------------------------- |
| 208 | */ |
| 209 | func errata_a57_826977_wa |
| 210 | /* |
| 211 | * Compare x0 against revision r1p1 |
| 212 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 213 | mov x17, x30 |
| 214 | bl check_errata_826977 |
| 215 | cbz x0, 1f |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 216 | mrs x1, CPUACTLR_EL1 |
| 217 | orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE |
| 218 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 219 | 1: |
| 220 | ret x17 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 221 | endfunc errata_a57_826977_wa |
| 222 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 223 | func check_errata_826977 |
| 224 | mov x1, #0x11 |
| 225 | b cpu_rev_var_ls |
| 226 | endfunc check_errata_826977 |
| 227 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 228 | /* --------------------------------------------------- |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 229 | * Errata Workaround for Cortex A57 Errata #828024. |
| 230 | * This applies only to revision <= r1p1 of Cortex A57. |
| 231 | * Inputs: |
| 232 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 233 | * Shall clobber: x0-x17 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 234 | * --------------------------------------------------- |
| 235 | */ |
| 236 | func errata_a57_828024_wa |
| 237 | /* |
| 238 | * Compare x0 against revision r1p1 |
| 239 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 240 | mov x17, x30 |
| 241 | bl check_errata_828024 |
| 242 | cbz x0, 1f |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 243 | mrs x1, CPUACTLR_EL1 |
| 244 | /* |
| 245 | * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 |
| 246 | * instructions here because the resulting bitmask doesn't fit in a |
| 247 | * 16-bit value so it cannot be encoded in a single instruction. |
| 248 | */ |
| 249 | orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA |
| 250 | orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) |
| 251 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 252 | 1: |
| 253 | ret x17 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 254 | endfunc errata_a57_828024_wa |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 255 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 256 | func check_errata_828024 |
| 257 | mov x1, #0x11 |
| 258 | b cpu_rev_var_ls |
| 259 | endfunc check_errata_828024 |
| 260 | |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 261 | /* --------------------------------------------------- |
| 262 | * Errata Workaround for Cortex A57 Errata #829520. |
| 263 | * This applies only to revision <= r1p2 of Cortex A57. |
| 264 | * Inputs: |
| 265 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 266 | * Shall clobber: x0-x17 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 267 | * --------------------------------------------------- |
| 268 | */ |
| 269 | func errata_a57_829520_wa |
| 270 | /* |
| 271 | * Compare x0 against revision r1p2 |
| 272 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 273 | mov x17, x30 |
| 274 | bl check_errata_829520 |
| 275 | cbz x0, 1f |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 276 | mrs x1, CPUACTLR_EL1 |
| 277 | orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR |
| 278 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 279 | 1: |
| 280 | ret x17 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 281 | endfunc errata_a57_829520_wa |
| 282 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 283 | func check_errata_829520 |
| 284 | mov x1, #0x12 |
| 285 | b cpu_rev_var_ls |
| 286 | endfunc check_errata_829520 |
| 287 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 288 | /* --------------------------------------------------- |
| 289 | * Errata Workaround for Cortex A57 Errata #833471. |
| 290 | * This applies only to revision <= r1p2 of Cortex A57. |
| 291 | * Inputs: |
| 292 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 293 | * Shall clobber: x0-x17 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 294 | * --------------------------------------------------- |
| 295 | */ |
| 296 | func errata_a57_833471_wa |
| 297 | /* |
| 298 | * Compare x0 against revision r1p2 |
| 299 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 300 | mov x17, x30 |
| 301 | bl check_errata_833471 |
| 302 | cbz x0, 1f |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 303 | mrs x1, CPUACTLR_EL1 |
| 304 | orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH |
| 305 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 306 | 1: |
| 307 | ret x17 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 308 | endfunc errata_a57_833471_wa |
| 309 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 310 | func check_errata_833471 |
| 311 | mov x1, #0x12 |
| 312 | b cpu_rev_var_ls |
| 313 | endfunc check_errata_833471 |
| 314 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 315 | /* ------------------------------------------------- |
| 316 | * The CPU Ops reset function for Cortex-A57. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 317 | * Shall clobber: x0-x19 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 318 | * ------------------------------------------------- |
| 319 | */ |
| 320 | func cortex_a57_reset_func |
| 321 | mov x19, x30 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 322 | bl cpu_get_rev_var |
| 323 | mov x18, x0 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 324 | |
| 325 | #if ERRATA_A57_806969 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 326 | mov x0, x18 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 327 | bl errata_a57_806969_wa |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 328 | #endif |
| 329 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 330 | #if ERRATA_A57_813420 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 331 | mov x0, x18 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 332 | bl errata_a57_813420_wa |
| 333 | #endif |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 334 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 335 | #if A57_DISABLE_NON_TEMPORAL_HINT |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 336 | mov x0, x18 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 337 | bl a57_disable_ldnp_overread |
| 338 | #endif |
| 339 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 340 | #if ERRATA_A57_826974 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 341 | mov x0, x18 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 342 | bl errata_a57_826974_wa |
| 343 | #endif |
| 344 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 345 | #if ERRATA_A57_826977 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 346 | mov x0, x18 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 347 | bl errata_a57_826977_wa |
| 348 | #endif |
| 349 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 350 | #if ERRATA_A57_828024 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 351 | mov x0, x18 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 352 | bl errata_a57_828024_wa |
| 353 | #endif |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 354 | |
| 355 | #if ERRATA_A57_829520 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 356 | mov x0, x18 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 357 | bl errata_a57_829520_wa |
| 358 | #endif |
| 359 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 360 | #if ERRATA_A57_833471 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 361 | mov x0, x18 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 362 | bl errata_a57_833471_wa |
| 363 | #endif |
| 364 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 365 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 366 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 367 | * --------------------------------------------- |
| 368 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 369 | mrs x0, CPUECTLR_EL1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 370 | orr x0, x0, #CPUECTLR_SMP_BIT |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 371 | msr CPUECTLR_EL1, x0 |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 372 | isb |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 373 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 374 | endfunc cortex_a57_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 375 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 376 | /* ---------------------------------------------------- |
| 377 | * The CPU Ops core power down function for Cortex-A57. |
| 378 | * ---------------------------------------------------- |
| 379 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 380 | func cortex_a57_core_pwr_dwn |
| 381 | mov x18, x30 |
| 382 | |
| 383 | /* --------------------------------------------- |
| 384 | * Turn off caches. |
| 385 | * --------------------------------------------- |
| 386 | */ |
| 387 | bl cortex_a57_disable_dcache |
| 388 | |
| 389 | /* --------------------------------------------- |
| 390 | * Disable the L2 prefetches. |
| 391 | * --------------------------------------------- |
| 392 | */ |
| 393 | bl cortex_a57_disable_l2_prefetch |
| 394 | |
| 395 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 396 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 397 | * --------------------------------------------- |
| 398 | */ |
| 399 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 400 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 401 | |
| 402 | /* --------------------------------------------- |
| 403 | * Come out of intra cluster coherency |
| 404 | * --------------------------------------------- |
| 405 | */ |
| 406 | bl cortex_a57_disable_smp |
| 407 | |
| 408 | /* --------------------------------------------- |
| 409 | * Force the debug interfaces to be quiescent |
| 410 | * --------------------------------------------- |
| 411 | */ |
| 412 | mov x30, x18 |
| 413 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 414 | endfunc cortex_a57_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 415 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 416 | /* ------------------------------------------------------- |
| 417 | * The CPU Ops cluster power down function for Cortex-A57. |
| 418 | * ------------------------------------------------------- |
| 419 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 420 | func cortex_a57_cluster_pwr_dwn |
| 421 | mov x18, x30 |
| 422 | |
| 423 | /* --------------------------------------------- |
| 424 | * Turn off caches. |
| 425 | * --------------------------------------------- |
| 426 | */ |
| 427 | bl cortex_a57_disable_dcache |
| 428 | |
| 429 | /* --------------------------------------------- |
| 430 | * Disable the L2 prefetches. |
| 431 | * --------------------------------------------- |
| 432 | */ |
| 433 | bl cortex_a57_disable_l2_prefetch |
| 434 | |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 435 | #if !SKIP_A57_L1_FLUSH_PWR_DWN |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 436 | /* ------------------------------------------------- |
| 437 | * Flush the L1 caches. |
| 438 | * ------------------------------------------------- |
| 439 | */ |
| 440 | mov x0, #DCCISW |
| 441 | bl dcsw_op_level1 |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 442 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 443 | /* --------------------------------------------- |
| 444 | * Disable the optional ACP. |
| 445 | * --------------------------------------------- |
| 446 | */ |
| 447 | bl plat_disable_acp |
| 448 | |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 449 | /* ------------------------------------------------- |
| 450 | * Flush the L2 caches. |
| 451 | * ------------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 452 | */ |
| 453 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 454 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 455 | |
| 456 | /* --------------------------------------------- |
| 457 | * Come out of intra cluster coherency |
| 458 | * --------------------------------------------- |
| 459 | */ |
| 460 | bl cortex_a57_disable_smp |
| 461 | |
| 462 | /* --------------------------------------------- |
| 463 | * Force the debug interfaces to be quiescent |
| 464 | * --------------------------------------------- |
| 465 | */ |
| 466 | mov x30, x18 |
| 467 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 468 | endfunc cortex_a57_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 469 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 470 | #if REPORT_ERRATA |
| 471 | /* |
| 472 | * Errata printing function for Cortex A57. Must follow AAPCS. |
| 473 | */ |
| 474 | func cortex_a57_errata_report |
| 475 | stp x8, x30, [sp, #-16]! |
| 476 | |
| 477 | bl cpu_get_rev_var |
| 478 | mov x8, x0 |
| 479 | |
| 480 | /* |
| 481 | * Report all errata. The revision-variant information is passed to |
| 482 | * checking functions of each errata. |
| 483 | */ |
| 484 | report_errata ERRATA_A57_806969, cortex_a57, 806969 |
| 485 | report_errata ERRATA_A57_813420, cortex_a57, 813420 |
| 486 | report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ |
| 487 | disable_ldnp_overread |
| 488 | report_errata ERRATA_A57_826974, cortex_a57, 826974 |
| 489 | report_errata ERRATA_A57_826977, cortex_a57, 826977 |
| 490 | report_errata ERRATA_A57_828024, cortex_a57, 828024 |
| 491 | report_errata ERRATA_A57_829520, cortex_a57, 829520 |
| 492 | report_errata ERRATA_A57_833471, cortex_a57, 833471 |
| 493 | |
| 494 | ldp x8, x30, [sp], #16 |
| 495 | ret |
| 496 | endfunc cortex_a57_errata_report |
| 497 | #endif |
| 498 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 499 | /* --------------------------------------------- |
| 500 | * This function provides cortex_a57 specific |
| 501 | * register information for crash reporting. |
| 502 | * It needs to return with x6 pointing to |
| 503 | * a list of register names in ascii and |
| 504 | * x8 - x15 having values of registers to be |
| 505 | * reported. |
| 506 | * --------------------------------------------- |
| 507 | */ |
| 508 | .section .rodata.cortex_a57_regs, "aS" |
| 509 | cortex_a57_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 510 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 511 | |
| 512 | func cortex_a57_cpu_reg_dump |
| 513 | adr x6, cortex_a57_regs |
| 514 | mrs x8, CPUECTLR_EL1 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 515 | mrs x9, CPUMERRSR_EL1 |
| 516 | mrs x10, L2MERRSR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 517 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 518 | endfunc cortex_a57_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 519 | |
| 520 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 521 | declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ |
| 522 | cortex_a57_reset_func, \ |
| 523 | cortex_a57_core_pwr_dwn, \ |
| 524 | cortex_a57_cluster_pwr_dwn |