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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Madhukar Pappireddye108df22023-03-22 15:40:40 -05002 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
Dan Handley9df48042015-03-19 18:58:55 +00009#include <arch.h>
10#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/bl_common.h>
12#include <common/debug.h>
13#include <drivers/console.h>
Ambroise Vincent9660dc12019-07-12 13:47:03 +010014#include <lib/debugfs.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/extensions/ras.h>
johpow019d134022021-06-16 17:57:28 -050016#include <lib/gpt_rme/gpt_rme.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/mmio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000019#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <plat/common/platform.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000021#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022
Dan Handley9df48042015-03-19 18:58:55 +000023/*
24 * Placeholder variables for copying the arguments that have been passed to
Juan Castillo7d199412015-12-14 09:35:25 +000025 * BL31 from BL2.
Dan Handley9df48042015-03-19 18:58:55 +000026 */
27static entry_point_info_t bl32_image_ep_info;
28static entry_point_info_t bl33_image_ep_info;
Zelalem Aweke96c0bab2021-07-11 18:39:39 -050029#if ENABLE_RME
30static entry_point_info_t rmm_image_ep_info;
31#endif
Dan Handley9df48042015-03-19 18:58:55 +000032
Soby Mathew7823d9e2018-10-14 08:13:44 +010033#if !RESET_TO_BL31
Soby Mathewaf14b462018-06-01 16:53:38 +010034/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010035 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
Soby Mathewaf14b462018-06-01 16:53:38 +010036 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
37 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010038CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
Soby Mathew7823d9e2018-10-14 08:13:44 +010039#endif
Dan Handley9df48042015-03-19 18:58:55 +000040
41/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000042#pragma weak bl31_early_platform_setup2
Dan Handley9df48042015-03-19 18:58:55 +000043#pragma weak bl31_platform_setup
44#pragma weak bl31_plat_arch_setup
45#pragma weak bl31_plat_get_next_image_ep_info
Madhukar Pappireddye108df22023-03-22 15:40:40 -050046#pragma weak bl31_plat_runtime_setup
Dan Handley9df48042015-03-19 18:58:55 +000047
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010048#define MAP_BL31_TOTAL MAP_REGION_FLAT( \
Soby Mathew7823d9e2018-10-14 08:13:44 +010049 BL31_START, \
50 BL31_END - BL31_START, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050051 MT_MEMORY | MT_RW | EL3_PAS)
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010052#if RECLAIM_INIT_CODE
53IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE);
Alexei Fedorov2a0c36f2020-07-21 17:07:45 +010054IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED);
David Horstmann8f15ca32020-10-14 15:17:49 +010055IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED);
Alexei Fedorov2a0c36f2020-07-21 17:07:45 +010056
57#define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \
58 ~(PAGE_SIZE - 1))
David Horstmann8f15ca32020-10-14 15:17:49 +010059#define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \
60 ~(PAGE_SIZE - 1))
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010061
62#define MAP_BL_INIT_CODE MAP_REGION_FLAT( \
63 BL_INIT_CODE_BASE, \
64 BL_INIT_CODE_END \
65 - BL_INIT_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050066 MT_CODE | EL3_PAS)
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010067#endif
Dan Handley9df48042015-03-19 18:58:55 +000068
Madhukar Pappireddyd7419442020-01-27 15:38:26 -060069#if SEPARATE_NOBITS_REGION
70#define MAP_BL31_NOBITS MAP_REGION_FLAT( \
71 BL31_NOBITS_BASE, \
72 BL31_NOBITS_LIMIT \
73 - BL31_NOBITS_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050074 MT_MEMORY | MT_RW | EL3_PAS)
Madhukar Pappireddyd7419442020-01-27 15:38:26 -060075
76#endif
Dan Handley9df48042015-03-19 18:58:55 +000077/*******************************************************************************
78 * Return a pointer to the 'entry_point_info' structure of the next image for the
Juan Castillo7d199412015-12-14 09:35:25 +000079 * security state specified. BL33 corresponds to the non-secure image type
80 * while BL32 corresponds to the secure image type. A NULL pointer is returned
Dan Handley9df48042015-03-19 18:58:55 +000081 * if the image does not exist.
82 ******************************************************************************/
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020083struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
Dan Handley9df48042015-03-19 18:58:55 +000084{
85 entry_point_info_t *next_image_info;
86
87 assert(sec_state_is_valid(type));
Zelalem Aweke96c0bab2021-07-11 18:39:39 -050088 if (type == NON_SECURE) {
89 next_image_info = &bl33_image_ep_info;
90 }
91#if ENABLE_RME
92 else if (type == REALM) {
93 next_image_info = &rmm_image_ep_info;
94 }
95#endif
96 else {
97 next_image_info = &bl32_image_ep_info;
98 }
99
Dan Handley9df48042015-03-19 18:58:55 +0000100 /*
101 * None of the images on the ARM development platforms can have 0x0
102 * as the entrypoint
103 */
104 if (next_image_info->pc)
105 return next_image_info;
106 else
107 return NULL;
108}
109
110/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000111 * Perform any BL31 early platform setup common to ARM standard platforms.
Dan Handley9df48042015-03-19 18:58:55 +0000112 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
John Tsichritzisd653d332018-09-14 10:34:57 +0100113 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
Dan Handley9df48042015-03-19 18:58:55 +0000114 * done before the MMU is initialized so that the memory layout can be used
115 * while creating page tables. BL2 has flushed this information to memory, so
116 * we are guaranteed to pick up good data.
117 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100118void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000119 uintptr_t hw_config, void *plat_params_from_bl2)
Dan Handley9df48042015-03-19 18:58:55 +0000120{
121 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100122 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +0000123
124#if RESET_TO_BL31
Juan Castillo7d199412015-12-14 09:35:25 +0000125 /* There are no parameters from BL2 if BL31 is a reset vector */
Dan Handley9df48042015-03-19 18:58:55 +0000126 assert(from_bl2 == NULL);
127 assert(plat_params_from_bl2 == NULL);
128
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100129# ifdef BL32_BASE
Juan Castillo7d199412015-12-14 09:35:25 +0000130 /* Populate entry point information for BL32 */
Dan Handley9df48042015-03-19 18:58:55 +0000131 SET_PARAM_HEAD(&bl32_image_ep_info,
132 PARAM_EP,
133 VERSION_1,
134 0);
135 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
136 bl32_image_ep_info.pc = BL32_BASE;
137 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
Manish Pandey18a0c3e2020-07-16 00:38:59 +0100138
139#if defined(SPD_spmd)
140 /* SPM (hafnium in secure world) expects SPM Core manifest base address
141 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared
142 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non
143 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest
144 * keep it in the last page.
145 */
146 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE +
147 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE;
148#endif
149
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100150# endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000151
Juan Castillo7d199412015-12-14 09:35:25 +0000152 /* Populate entry point information for BL33 */
Dan Handley9df48042015-03-19 18:58:55 +0000153 SET_PARAM_HEAD(&bl33_image_ep_info,
154 PARAM_EP,
155 VERSION_1,
156 0);
157 /*
Juan Castillo7d199412015-12-14 09:35:25 +0000158 * Tell BL31 where the non-trusted software image
Dan Handley9df48042015-03-19 18:58:55 +0000159 * is located and the entry state information
160 */
161 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
Soby Mathew4876ae32016-05-09 17:20:10 +0100162
Dan Handley9df48042015-03-19 18:58:55 +0000163 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
164 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
165
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000166#if ENABLE_RME
167 /*
168 * Populate entry point information for RMM.
169 * Only PC needs to be set as other fields are determined by RMMD.
170 */
171 rmm_image_ep_info.pc = RMM_BASE;
172#endif /* ENABLE_RME */
173
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100174#else /* RESET_TO_BL31 */
175
Dan Handley9df48042015-03-19 18:58:55 +0000176 /*
177 * In debug builds, we pass a special value in 'plat_params_from_bl2'
Juan Castillo7d199412015-12-14 09:35:25 +0000178 * to verify platform parameters from BL2 to BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000179 * In release builds, it's not used.
180 */
181 assert(((unsigned long long)plat_params_from_bl2) ==
182 ARM_BL31_PLAT_PARAM_VAL);
183
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100184 /*
185 * Check params passed from BL2 should not be NULL,
186 */
187 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
188 assert(params_from_bl2 != NULL);
189 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
190 assert(params_from_bl2->h.version >= VERSION_2);
191
192 bl_params_node_t *bl_params = params_from_bl2->head;
193
194 /*
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500195 * Copy BL33, BL32 and RMM (if present), entry point information.
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100196 * They are stored in Secure RAM, in BL2's address space.
197 */
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100198 while (bl_params != NULL) {
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500199 if (bl_params->image_id == BL32_IMAGE_ID) {
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100200 bl32_image_ep_info = *bl_params->ep_info;
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500201 }
202#if ENABLE_RME
203 else if (bl_params->image_id == RMM_IMAGE_ID) {
204 rmm_image_ep_info = *bl_params->ep_info;
205 }
206#endif
207 else if (bl_params->image_id == BL33_IMAGE_ID) {
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100208 bl33_image_ep_info = *bl_params->ep_info;
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500209 }
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100210
211 bl_params = bl_params->next_params_info;
212 }
213
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100214 if (bl33_image_ep_info.pc == 0U)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100215 panic();
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500216#if ENABLE_RME
217 if (rmm_image_ep_info.pc == 0U)
218 panic();
219#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100220#endif /* RESET_TO_BL31 */
Andre Przywara0f58c8a2021-02-08 17:40:17 +0000221
222# if ARM_LINUX_KERNEL_AS_BL33
223 /*
224 * According to the file ``Documentation/arm64/booting.txt`` of the
225 * Linux kernel tree, Linux expects the physical address of the device
226 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
227 * must be 0.
Olivier Deprez735ac782021-10-20 15:17:07 +0200228 * Repurpose the option to load Hafnium hypervisor in the normal world.
229 * It expects its manifest address in x0. This is essentially the linux
230 * dts (passed to the primary VM) by adding 'hypervisor' and chosen
231 * nodes specifying the Hypervisor configuration.
Andre Przywara0f58c8a2021-02-08 17:40:17 +0000232 */
Zelalem Aweke1e8e3fd2021-07-26 21:39:05 -0500233#if RESET_TO_BL31
Andre Przywara0f58c8a2021-02-08 17:40:17 +0000234 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
Zelalem Aweke1e8e3fd2021-07-26 21:39:05 -0500235#else
236 bl33_image_ep_info.args.arg0 = (u_register_t)hw_config;
237#endif
Andre Przywara0f58c8a2021-02-08 17:40:17 +0000238 bl33_image_ep_info.args.arg1 = 0U;
239 bl33_image_ep_info.args.arg2 = 0U;
240 bl33_image_ep_info.args.arg3 = 0U;
241# endif
Dan Handley9df48042015-03-19 18:58:55 +0000242}
243
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000244void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
245 u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +0000246{
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000247 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
Dan Handley9df48042015-03-19 18:58:55 +0000248
249 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000250 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +0000251 * No need for locks as no other CPU is active.
252 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000253 plat_arm_interconnect_init();
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100254
Dan Handley9df48042015-03-19 18:58:55 +0000255 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000256 * Enable Interconnect coherency for the primary CPU's cluster.
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100257 * Earlier bootloader stages might already do this (e.g. Trusted
258 * Firmware's BL1 does it) but we can't assume so. There is no harm in
259 * executing this code twice anyway.
Dan Handley9df48042015-03-19 18:58:55 +0000260 * Platform specific PSCI code will enable coherency for other
261 * clusters.
262 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000263 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000264}
265
266/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000267 * Perform any BL31 platform setup common to ARM standard platforms
Dan Handley9df48042015-03-19 18:58:55 +0000268 ******************************************************************************/
269void arm_bl31_platform_setup(void)
270{
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000271 /* Initialize the GIC driver, cpu and distributor interfaces */
272 plat_arm_gic_driver_init();
Dan Handley9df48042015-03-19 18:58:55 +0000273 plat_arm_gic_init();
Dan Handley9df48042015-03-19 18:58:55 +0000274
275#if RESET_TO_BL31
276 /*
277 * Do initial security configuration to allow DRAM/device access
278 * (if earlier BL has not already done so).
279 */
280 plat_arm_security_setup();
281
Roberto Vargas550eb082018-01-05 16:00:05 +0000282#if defined(PLAT_ARM_MEM_PROT_ADDR)
283 arm_nor_psci_do_dyn_mem_protect();
284#endif /* PLAT_ARM_MEM_PROT_ADDR */
285
Dan Handley9df48042015-03-19 18:58:55 +0000286#endif /* RESET_TO_BL31 */
287
288 /* Enable and initialize the System level generic timer */
289 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100290 CNTCR_FCREQ(0U) | CNTCR_EN);
Dan Handley9df48042015-03-19 18:58:55 +0000291
292 /* Allow access to the System counter timer module */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100293 arm_configure_sys_timer();
Dan Handley9df48042015-03-19 18:58:55 +0000294
295 /* Initialize power controller before setting up topology */
296 plat_arm_pwrc_setup();
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000297
Manish Pandeyd419e222023-02-13 12:39:17 +0000298#if RAS_FFH_SUPPORT
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000299 ras_init();
300#endif
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100301
302#if USE_DEBUGFS
303 debugfs_init();
304#endif /* USE_DEBUGFS */
Dan Handley9df48042015-03-19 18:58:55 +0000305}
306
Soby Mathew2fd66be2015-12-09 11:38:43 +0000307/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000308 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM
Soby Mathew2fd66be2015-12-09 11:38:43 +0000309 * standard platforms
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100310 * Perform BL31 platform setup
Soby Mathew2fd66be2015-12-09 11:38:43 +0000311 ******************************************************************************/
312void arm_bl31_plat_runtime_setup(void)
313{
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100314 console_switch_state(CONSOLE_FLAG_RUNTIME);
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100315
Soby Mathew2fd66be2015-12-09 11:38:43 +0000316 /* Initialize the runtime console */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100317 arm_console_runtime_init();
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000318
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100319#if RECLAIM_INIT_CODE
320 arm_free_init_memory();
321#endif
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000322
323#if PLAT_RO_XLAT_TABLES
324 arm_xlat_make_tables_readonly();
325#endif
Soby Mathew2fd66be2015-12-09 11:38:43 +0000326}
327
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100328#if RECLAIM_INIT_CODE
329/*
David Horstmann8f15ca32020-10-14 15:17:49 +0100330 * Make memory for image boot time code RW to reclaim it as stack for the
331 * secondary cores, or RO where it cannot be reclaimed:
332 *
333 * |-------- INIT SECTION --------|
334 * -----------------------------------------
335 * | CORE 0 | CORE 1 | CORE 2 | EXTRA |
336 * | STACK | STACK | STACK | SPACE |
337 * -----------------------------------------
338 * <-------------------> <------>
339 * MAKE RW AND XN MAKE
340 * FOR STACKS RO AND XN
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100341 */
342void arm_free_init_memory(void)
343{
David Horstmann8f15ca32020-10-14 15:17:49 +0100344 int ret = 0;
345
346 if (BL_STACKS_END < BL_INIT_CODE_END) {
347 /* Reclaim some of the init section as stack if possible. */
348 if (BL_INIT_CODE_BASE < BL_STACKS_END) {
349 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
350 BL_STACKS_END - BL_INIT_CODE_BASE,
351 MT_RW_DATA);
352 }
353 /* Make the rest of the init section read-only. */
354 ret |= xlat_change_mem_attributes(BL_STACKS_END,
355 BL_INIT_CODE_END - BL_STACKS_END,
356 MT_RO_DATA);
357 } else {
358 /* The stacks cover the init section, so reclaim it all. */
359 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100360 BL_INIT_CODE_END - BL_INIT_CODE_BASE,
361 MT_RW_DATA);
David Horstmann8f15ca32020-10-14 15:17:49 +0100362 }
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100363
364 if (ret != 0) {
365 ERROR("Could not reclaim initialization code");
366 panic();
367 }
368}
369#endif
370
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100371void __init bl31_platform_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000372{
373 arm_bl31_platform_setup();
374}
375
Soby Mathew2fd66be2015-12-09 11:38:43 +0000376void bl31_plat_runtime_setup(void)
377{
378 arm_bl31_plat_runtime_setup();
379}
380
Dan Handley9df48042015-03-19 18:58:55 +0000381/*******************************************************************************
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100382 * Perform the very early platform specific architectural setup shared between
383 * ARM standard platforms. This only does basic initialization. Later
384 * architectural setup (bl31_arch_setup()) does not do anything platform
385 * specific.
Dan Handley9df48042015-03-19 18:58:55 +0000386 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100387void __init arm_bl31_plat_arch_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000388{
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100389 const mmap_region_t bl_regions[] = {
390 MAP_BL31_TOTAL,
Zelalem Awekec43c5632021-07-12 23:41:05 -0500391#if ENABLE_RME
392 ARM_MAP_L0_GPT_REGION,
393#endif
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100394#if RECLAIM_INIT_CODE
395 MAP_BL_INIT_CODE,
396#endif
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600397#if SEPARATE_NOBITS_REGION
398 MAP_BL31_NOBITS,
399#endif
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100400 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100401#if USE_ROMLIB
402 ARM_MAP_ROMLIB_CODE,
403 ARM_MAP_ROMLIB_DATA,
404#endif
Dan Handley9df48042015-03-19 18:58:55 +0000405#if USE_COHERENT_MEM
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100406 ARM_MAP_BL_COHERENT_RAM,
Dan Handley9df48042015-03-19 18:58:55 +0000407#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100408 {0}
409 };
410
Roberto Vargas344ff022018-10-19 16:44:18 +0100411 setup_page_tables(bl_regions, plat_arm_get_mmap());
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100412
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100413 enable_mmu_el3(0);
Roberto Vargase3adc372018-05-23 09:27:06 +0100414
johpow019d134022021-06-16 17:57:28 -0500415#if ENABLE_RME
416 /*
417 * Initialise Granule Protection library and enable GPC for the primary
418 * processor. The tables have already been initialized by a previous BL
419 * stage, so there is no need to provide any PAS here. This function
420 * sets up pointers to those tables.
421 */
422 if (gpt_runtime_init() < 0) {
423 ERROR("gpt_runtime_init() failed!\n");
424 panic();
425 }
426#endif /* ENABLE_RME */
427
Roberto Vargase3adc372018-05-23 09:27:06 +0100428 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000429}
430
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100431void __init bl31_plat_arch_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000432{
433 arm_bl31_plat_arch_setup();
434}