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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Zelalem Aweke96c0bab2021-07-11 18:39:39 -05002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
Dan Handley9df48042015-03-19 18:58:55 +00009#include <arch.h>
10#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/bl_common.h>
12#include <common/debug.h>
13#include <drivers/console.h>
Ambroise Vincent9660dc12019-07-12 13:47:03 +010014#include <lib/debugfs.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/extensions/ras.h>
16#include <lib/mmio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000018#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <plat/common/platform.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000020#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021
Dan Handley9df48042015-03-19 18:58:55 +000022/*
23 * Placeholder variables for copying the arguments that have been passed to
Juan Castillo7d199412015-12-14 09:35:25 +000024 * BL31 from BL2.
Dan Handley9df48042015-03-19 18:58:55 +000025 */
26static entry_point_info_t bl32_image_ep_info;
27static entry_point_info_t bl33_image_ep_info;
Zelalem Aweke96c0bab2021-07-11 18:39:39 -050028#if ENABLE_RME
29static entry_point_info_t rmm_image_ep_info;
30#endif
Dan Handley9df48042015-03-19 18:58:55 +000031
Soby Mathew7823d9e2018-10-14 08:13:44 +010032#if !RESET_TO_BL31
Soby Mathewaf14b462018-06-01 16:53:38 +010033/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010034 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
Soby Mathewaf14b462018-06-01 16:53:38 +010035 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
36 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010037CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
Soby Mathew7823d9e2018-10-14 08:13:44 +010038#endif
Dan Handley9df48042015-03-19 18:58:55 +000039
40/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000041#pragma weak bl31_early_platform_setup2
Dan Handley9df48042015-03-19 18:58:55 +000042#pragma weak bl31_platform_setup
43#pragma weak bl31_plat_arch_setup
44#pragma weak bl31_plat_get_next_image_ep_info
Dan Handley9df48042015-03-19 18:58:55 +000045
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010046#define MAP_BL31_TOTAL MAP_REGION_FLAT( \
Soby Mathew7823d9e2018-10-14 08:13:44 +010047 BL31_START, \
48 BL31_END - BL31_START, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050049 MT_MEMORY | MT_RW | EL3_PAS)
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010050#if RECLAIM_INIT_CODE
51IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE);
Alexei Fedorov2a0c36f2020-07-21 17:07:45 +010052IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED);
David Horstmann8f15ca32020-10-14 15:17:49 +010053IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED);
Alexei Fedorov2a0c36f2020-07-21 17:07:45 +010054
55#define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \
56 ~(PAGE_SIZE - 1))
David Horstmann8f15ca32020-10-14 15:17:49 +010057#define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \
58 ~(PAGE_SIZE - 1))
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010059
60#define MAP_BL_INIT_CODE MAP_REGION_FLAT( \
61 BL_INIT_CODE_BASE, \
62 BL_INIT_CODE_END \
63 - BL_INIT_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050064 MT_CODE | EL3_PAS)
Daniel Boulbyb1b058d2018-09-18 11:52:49 +010065#endif
Dan Handley9df48042015-03-19 18:58:55 +000066
Madhukar Pappireddyd7419442020-01-27 15:38:26 -060067#if SEPARATE_NOBITS_REGION
68#define MAP_BL31_NOBITS MAP_REGION_FLAT( \
69 BL31_NOBITS_BASE, \
70 BL31_NOBITS_LIMIT \
71 - BL31_NOBITS_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050072 MT_MEMORY | MT_RW | EL3_PAS)
Madhukar Pappireddyd7419442020-01-27 15:38:26 -060073
74#endif
Dan Handley9df48042015-03-19 18:58:55 +000075/*******************************************************************************
76 * Return a pointer to the 'entry_point_info' structure of the next image for the
Juan Castillo7d199412015-12-14 09:35:25 +000077 * security state specified. BL33 corresponds to the non-secure image type
78 * while BL32 corresponds to the secure image type. A NULL pointer is returned
Dan Handley9df48042015-03-19 18:58:55 +000079 * if the image does not exist.
80 ******************************************************************************/
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020081struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
Dan Handley9df48042015-03-19 18:58:55 +000082{
83 entry_point_info_t *next_image_info;
84
85 assert(sec_state_is_valid(type));
Zelalem Aweke96c0bab2021-07-11 18:39:39 -050086 if (type == NON_SECURE) {
87 next_image_info = &bl33_image_ep_info;
88 }
89#if ENABLE_RME
90 else if (type == REALM) {
91 next_image_info = &rmm_image_ep_info;
92 }
93#endif
94 else {
95 next_image_info = &bl32_image_ep_info;
96 }
97
Dan Handley9df48042015-03-19 18:58:55 +000098 /*
99 * None of the images on the ARM development platforms can have 0x0
100 * as the entrypoint
101 */
102 if (next_image_info->pc)
103 return next_image_info;
104 else
105 return NULL;
106}
107
108/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000109 * Perform any BL31 early platform setup common to ARM standard platforms.
Dan Handley9df48042015-03-19 18:58:55 +0000110 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
John Tsichritzisd653d332018-09-14 10:34:57 +0100111 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
Dan Handley9df48042015-03-19 18:58:55 +0000112 * done before the MMU is initialized so that the memory layout can be used
113 * while creating page tables. BL2 has flushed this information to memory, so
114 * we are guaranteed to pick up good data.
115 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100116void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000117 uintptr_t hw_config, void *plat_params_from_bl2)
Dan Handley9df48042015-03-19 18:58:55 +0000118{
119 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100120 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +0000121
122#if RESET_TO_BL31
Juan Castillo7d199412015-12-14 09:35:25 +0000123 /* There are no parameters from BL2 if BL31 is a reset vector */
Dan Handley9df48042015-03-19 18:58:55 +0000124 assert(from_bl2 == NULL);
125 assert(plat_params_from_bl2 == NULL);
126
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100127# ifdef BL32_BASE
Juan Castillo7d199412015-12-14 09:35:25 +0000128 /* Populate entry point information for BL32 */
Dan Handley9df48042015-03-19 18:58:55 +0000129 SET_PARAM_HEAD(&bl32_image_ep_info,
130 PARAM_EP,
131 VERSION_1,
132 0);
133 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
134 bl32_image_ep_info.pc = BL32_BASE;
135 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
Manish Pandey18a0c3e2020-07-16 00:38:59 +0100136
137#if defined(SPD_spmd)
138 /* SPM (hafnium in secure world) expects SPM Core manifest base address
139 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared
140 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non
141 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest
142 * keep it in the last page.
143 */
144 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE +
145 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE;
146#endif
147
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100148# endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000149
Juan Castillo7d199412015-12-14 09:35:25 +0000150 /* Populate entry point information for BL33 */
Dan Handley9df48042015-03-19 18:58:55 +0000151 SET_PARAM_HEAD(&bl33_image_ep_info,
152 PARAM_EP,
153 VERSION_1,
154 0);
155 /*
Juan Castillo7d199412015-12-14 09:35:25 +0000156 * Tell BL31 where the non-trusted software image
Dan Handley9df48042015-03-19 18:58:55 +0000157 * is located and the entry state information
158 */
159 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
Soby Mathew4876ae32016-05-09 17:20:10 +0100160
Dan Handley9df48042015-03-19 18:58:55 +0000161 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
162 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
163
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100164#else /* RESET_TO_BL31 */
165
Dan Handley9df48042015-03-19 18:58:55 +0000166 /*
167 * In debug builds, we pass a special value in 'plat_params_from_bl2'
Juan Castillo7d199412015-12-14 09:35:25 +0000168 * to verify platform parameters from BL2 to BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000169 * In release builds, it's not used.
170 */
171 assert(((unsigned long long)plat_params_from_bl2) ==
172 ARM_BL31_PLAT_PARAM_VAL);
173
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100174 /*
175 * Check params passed from BL2 should not be NULL,
176 */
177 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
178 assert(params_from_bl2 != NULL);
179 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
180 assert(params_from_bl2->h.version >= VERSION_2);
181
182 bl_params_node_t *bl_params = params_from_bl2->head;
183
184 /*
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500185 * Copy BL33, BL32 and RMM (if present), entry point information.
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100186 * They are stored in Secure RAM, in BL2's address space.
187 */
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100188 while (bl_params != NULL) {
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500189 if (bl_params->image_id == BL32_IMAGE_ID) {
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100190 bl32_image_ep_info = *bl_params->ep_info;
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500191 }
192#if ENABLE_RME
193 else if (bl_params->image_id == RMM_IMAGE_ID) {
194 rmm_image_ep_info = *bl_params->ep_info;
195 }
196#endif
197 else if (bl_params->image_id == BL33_IMAGE_ID) {
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100198 bl33_image_ep_info = *bl_params->ep_info;
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500199 }
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100200
201 bl_params = bl_params->next_params_info;
202 }
203
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100204 if (bl33_image_ep_info.pc == 0U)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100205 panic();
Zelalem Aweke96c0bab2021-07-11 18:39:39 -0500206#if ENABLE_RME
207 if (rmm_image_ep_info.pc == 0U)
208 panic();
209#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100210#endif /* RESET_TO_BL31 */
Andre Przywara0f58c8a2021-02-08 17:40:17 +0000211
212# if ARM_LINUX_KERNEL_AS_BL33
213 /*
214 * According to the file ``Documentation/arm64/booting.txt`` of the
215 * Linux kernel tree, Linux expects the physical address of the device
216 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
217 * must be 0.
218 */
219 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
220 bl33_image_ep_info.args.arg1 = 0U;
221 bl33_image_ep_info.args.arg2 = 0U;
222 bl33_image_ep_info.args.arg3 = 0U;
223# endif
Manish Pandeyea164e72021-04-09 16:18:41 +0100224
225#if defined(SPD_spmd)
226 /*
227 * Hafnium in normal world expects its manifest address in x0, In CI
228 * configuration manifest is preloaded at 0x80000000(start of DRAM).
229 */
230 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE;
231#endif
Dan Handley9df48042015-03-19 18:58:55 +0000232}
233
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000234void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
235 u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +0000236{
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000237 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
Dan Handley9df48042015-03-19 18:58:55 +0000238
239 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000240 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +0000241 * No need for locks as no other CPU is active.
242 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000243 plat_arm_interconnect_init();
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100244
Dan Handley9df48042015-03-19 18:58:55 +0000245 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000246 * Enable Interconnect coherency for the primary CPU's cluster.
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100247 * Earlier bootloader stages might already do this (e.g. Trusted
248 * Firmware's BL1 does it) but we can't assume so. There is no harm in
249 * executing this code twice anyway.
Dan Handley9df48042015-03-19 18:58:55 +0000250 * Platform specific PSCI code will enable coherency for other
251 * clusters.
252 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000253 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000254}
255
256/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000257 * Perform any BL31 platform setup common to ARM standard platforms
Dan Handley9df48042015-03-19 18:58:55 +0000258 ******************************************************************************/
259void arm_bl31_platform_setup(void)
260{
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000261 /* Initialize the GIC driver, cpu and distributor interfaces */
262 plat_arm_gic_driver_init();
Dan Handley9df48042015-03-19 18:58:55 +0000263 plat_arm_gic_init();
Dan Handley9df48042015-03-19 18:58:55 +0000264
265#if RESET_TO_BL31
266 /*
267 * Do initial security configuration to allow DRAM/device access
268 * (if earlier BL has not already done so).
269 */
270 plat_arm_security_setup();
271
Roberto Vargas550eb082018-01-05 16:00:05 +0000272#if defined(PLAT_ARM_MEM_PROT_ADDR)
273 arm_nor_psci_do_dyn_mem_protect();
274#endif /* PLAT_ARM_MEM_PROT_ADDR */
275
Dan Handley9df48042015-03-19 18:58:55 +0000276#endif /* RESET_TO_BL31 */
277
278 /* Enable and initialize the System level generic timer */
279 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
Antonio Nino Diaze0b757d2018-08-24 16:30:29 +0100280 CNTCR_FCREQ(0U) | CNTCR_EN);
Dan Handley9df48042015-03-19 18:58:55 +0000281
282 /* Allow access to the System counter timer module */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100283 arm_configure_sys_timer();
Dan Handley9df48042015-03-19 18:58:55 +0000284
285 /* Initialize power controller before setting up topology */
286 plat_arm_pwrc_setup();
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000287
288#if RAS_EXTENSION
289 ras_init();
290#endif
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100291
292#if USE_DEBUGFS
293 debugfs_init();
294#endif /* USE_DEBUGFS */
Dan Handley9df48042015-03-19 18:58:55 +0000295}
296
Soby Mathew2fd66be2015-12-09 11:38:43 +0000297/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000298 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM
Soby Mathew2fd66be2015-12-09 11:38:43 +0000299 * standard platforms
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100300 * Perform BL31 platform setup
Soby Mathew2fd66be2015-12-09 11:38:43 +0000301 ******************************************************************************/
302void arm_bl31_plat_runtime_setup(void)
303{
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100304 console_switch_state(CONSOLE_FLAG_RUNTIME);
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100305
Soby Mathew2fd66be2015-12-09 11:38:43 +0000306 /* Initialize the runtime console */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100307 arm_console_runtime_init();
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000308
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100309#if RECLAIM_INIT_CODE
310 arm_free_init_memory();
311#endif
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000312
313#if PLAT_RO_XLAT_TABLES
314 arm_xlat_make_tables_readonly();
315#endif
Soby Mathew2fd66be2015-12-09 11:38:43 +0000316}
317
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100318#if RECLAIM_INIT_CODE
319/*
David Horstmann8f15ca32020-10-14 15:17:49 +0100320 * Make memory for image boot time code RW to reclaim it as stack for the
321 * secondary cores, or RO where it cannot be reclaimed:
322 *
323 * |-------- INIT SECTION --------|
324 * -----------------------------------------
325 * | CORE 0 | CORE 1 | CORE 2 | EXTRA |
326 * | STACK | STACK | STACK | SPACE |
327 * -----------------------------------------
328 * <-------------------> <------>
329 * MAKE RW AND XN MAKE
330 * FOR STACKS RO AND XN
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100331 */
332void arm_free_init_memory(void)
333{
David Horstmann8f15ca32020-10-14 15:17:49 +0100334 int ret = 0;
335
336 if (BL_STACKS_END < BL_INIT_CODE_END) {
337 /* Reclaim some of the init section as stack if possible. */
338 if (BL_INIT_CODE_BASE < BL_STACKS_END) {
339 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
340 BL_STACKS_END - BL_INIT_CODE_BASE,
341 MT_RW_DATA);
342 }
343 /* Make the rest of the init section read-only. */
344 ret |= xlat_change_mem_attributes(BL_STACKS_END,
345 BL_INIT_CODE_END - BL_STACKS_END,
346 MT_RO_DATA);
347 } else {
348 /* The stacks cover the init section, so reclaim it all. */
349 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100350 BL_INIT_CODE_END - BL_INIT_CODE_BASE,
351 MT_RW_DATA);
David Horstmann8f15ca32020-10-14 15:17:49 +0100352 }
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100353
354 if (ret != 0) {
355 ERROR("Could not reclaim initialization code");
356 panic();
357 }
358}
359#endif
360
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100361void __init bl31_platform_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000362{
363 arm_bl31_platform_setup();
364}
365
Soby Mathew2fd66be2015-12-09 11:38:43 +0000366void bl31_plat_runtime_setup(void)
367{
368 arm_bl31_plat_runtime_setup();
369}
370
Dan Handley9df48042015-03-19 18:58:55 +0000371/*******************************************************************************
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100372 * Perform the very early platform specific architectural setup shared between
373 * ARM standard platforms. This only does basic initialization. Later
374 * architectural setup (bl31_arch_setup()) does not do anything platform
375 * specific.
Dan Handley9df48042015-03-19 18:58:55 +0000376 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100377void __init arm_bl31_plat_arch_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000378{
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100379 const mmap_region_t bl_regions[] = {
380 MAP_BL31_TOTAL,
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100381#if RECLAIM_INIT_CODE
382 MAP_BL_INIT_CODE,
383#endif
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600384#if SEPARATE_NOBITS_REGION
385 MAP_BL31_NOBITS,
386#endif
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100387 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100388#if USE_ROMLIB
389 ARM_MAP_ROMLIB_CODE,
390 ARM_MAP_ROMLIB_DATA,
391#endif
Dan Handley9df48042015-03-19 18:58:55 +0000392#if USE_COHERENT_MEM
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100393 ARM_MAP_BL_COHERENT_RAM,
Dan Handley9df48042015-03-19 18:58:55 +0000394#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100395 {0}
396 };
397
Roberto Vargas344ff022018-10-19 16:44:18 +0100398 setup_page_tables(bl_regions, plat_arm_get_mmap());
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100399
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100400 enable_mmu_el3(0);
Roberto Vargase3adc372018-05-23 09:27:06 +0100401
402 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000403}
404
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100405void __init bl31_plat_arch_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000406{
407 arm_bl31_plat_arch_setup();
408}