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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Roberto Vargas1a6eed32018-02-12 12:36:17 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Achin Gupta4f6ad662013-10-25 09:08:21 +01007#include <arch_helpers.h>
Dan Handley2b6b5742015-03-19 19:17:53 +00008#include <arm_config.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +01009#include <assert.h>
Juan Castillo4dc4a472014-08-12 11:17:06 +010010#include <debug.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000011#include <errno.h>
Soby Mathew9ca28062017-10-11 16:08:58 +010012#include <gicv3.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010013#include <mmio.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000014#include <plat_arm.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010015#include <platform.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010016#include <psci.h>
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010017#include <spe.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000018#include <v2m_def.h>
Roberto Vargas2ca18d92018-02-12 12:36:17 +000019#include "../../../../drivers/arm/gic/v3/gicv3_private.h"
Dan Handley4d2e49d2014-04-11 11:52:12 +010020#include "drivers/pwrc/fvp_pwrc.h"
Dan Handleyed6ff952014-05-14 17:44:19 +010021#include "fvp_def.h"
22#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010023
Dan Handley2b6b5742015-03-19 19:17:53 +000024
Soby Mathew7799cf72015-04-16 14:49:09 +010025#if ARM_RECOM_STATE_ID_ENC
26/*
27 * The table storing the valid idle power states. Ensure that the
28 * array entries are populated in ascending order of state-id to
29 * enable us to use binary search during power state validation.
30 * The table must be terminated by a NULL entry.
31 */
32const unsigned int arm_pm_idle_states[] = {
33 /* State-id - 0x01 */
34 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET,
35 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
36 /* State-id - 0x02 */
37 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
38 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
39 /* State-id - 0x22 */
40 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
41 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
Soby Mathew9ca28062017-10-11 16:08:58 +010042 /* State-id - 0x222 */
43 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
44 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
Soby Mathew7799cf72015-04-16 14:49:09 +010045 0,
46};
47#endif
48
Achin Gupta4f6ad662013-10-25 09:08:21 +010049/*******************************************************************************
Achin Gupta85876392014-07-31 17:45:51 +010050 * Function which implements the common FVP specific operations to power down a
Achin Gupta85876392014-07-31 17:45:51 +010051 * cluster in response to a CPU_OFF or CPU_SUSPEND request.
52 ******************************************************************************/
Sandrine Bailleuxa64a8542015-03-05 10:54:34 +000053static void fvp_cluster_pwrdwn_common(void)
Achin Gupta85876392014-07-31 17:45:51 +010054{
55 uint64_t mpidr = read_mpidr_el1();
56
dp-armee3457b2017-05-23 09:32:49 +010057#if ENABLE_SPE_FOR_LOWER_ELS
58 /*
59 * On power down we need to disable statistical profiling extensions
60 * before exiting coherency.
61 */
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010062 spe_disable();
dp-armee3457b2017-05-23 09:32:49 +010063#endif
64
Achin Gupta85876392014-07-31 17:45:51 +010065 /* Disable coherency if this cluster is to be turned off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000066 fvp_interconnect_disable();
Achin Gupta85876392014-07-31 17:45:51 +010067
68 /* Program the power controller to turn the cluster off */
69 fvp_pwrc_write_pcoffr(mpidr);
70}
71
Soby Mathew9ca28062017-10-11 16:08:58 +010072/*
73 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit
74 * on ARM GICv3 implementations on FVP. This is required, because FVP does not
75 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up
76 * from `fake` system suspend the GIC must not be powered off.
77 */
Roberto Vargas1a6eed32018-02-12 12:36:17 +000078void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num)
Soby Mathew9ca28062017-10-11 16:08:58 +010079{}
80
Roberto Vargas1a6eed32018-02-12 12:36:17 +000081void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num)
Soby Mathew9ca28062017-10-11 16:08:58 +010082{}
83
Soby Mathew12012dd2015-10-26 14:01:53 +000084static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state)
85{
86 unsigned long mpidr;
87
88 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
89 ARM_LOCAL_STATE_OFF);
90
91 /* Get the mpidr for this cpu */
92 mpidr = read_mpidr_el1();
93
94 /* Perform the common cluster specific operations */
95 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
96 ARM_LOCAL_STATE_OFF) {
97 /*
98 * This CPU might have woken up whilst the cluster was
99 * attempting to power down. In this case the FVP power
100 * controller will have a pending cluster power off request
101 * which needs to be cleared by writing to the PPONR register.
102 * This prevents the power controller from interpreting a
103 * subsequent entry of this cpu into a simple wfi as a power
104 * down request.
105 */
106 fvp_pwrc_write_pponr(mpidr);
107
108 /* Enable coherency if this cluster was off */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000109 fvp_interconnect_enable();
Soby Mathew12012dd2015-10-26 14:01:53 +0000110 }
Soby Mathew9ca28062017-10-11 16:08:58 +0100111 /* Perform the common system specific operations */
112 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
113 ARM_LOCAL_STATE_OFF)
114 arm_system_pwr_domain_resume();
Soby Mathew12012dd2015-10-26 14:01:53 +0000115
116 /*
117 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
118 * with a cpu power down unless the bit is set again
119 */
120 fvp_pwrc_clr_wen(mpidr);
121}
122
123
Achin Gupta85876392014-07-31 17:45:51 +0100124/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100125 * FVP handler called when a CPU is about to enter standby.
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000126 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000127static void fvp_cpu_standby(plat_local_state_t cpu_state)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000128{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100129
130 assert(cpu_state == ARM_LOCAL_STATE_RET);
131
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100132 /*
133 * Enter standby state
134 * dsb is good practice before using wfi to enter low power states
135 */
136 dsb();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000137 wfi();
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000138}
139
140/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100141 * FVP handler called when a power domain is about to be turned on. The
142 * mpidr determines the CPU to be turned on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100143 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000144static int fvp_pwr_domain_on(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100145{
146 int rc = PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147 unsigned int psysr;
148
Achin Gupta4f6ad662013-10-25 09:08:21 +0100149 /*
Sandrine Bailleux7175bde2015-12-08 14:18:24 +0000150 * Ensure that we do not cancel an inflight power off request for the
151 * target cpu. That would leave it in a zombie wfi. Wait for it to power
152 * off and then program the power controller to turn that CPU on.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100153 */
154 do {
155 psysr = fvp_pwrc_read_psysr(mpidr);
156 } while (psysr & PSYSR_AFF_L0);
157
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158 fvp_pwrc_write_pponr(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159 return rc;
160}
161
162/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100163 * FVP handler called when a power domain is about to be turned off. The
164 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100165 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000166static void fvp_pwr_domain_off(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100168 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
169 ARM_LOCAL_STATE_OFF);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100170
Achin Gupta85876392014-07-31 17:45:51 +0100171 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100172 * If execution reaches this stage then this power domain will be
173 * suspended. Perform at least the cpu specific actions followed
174 * by the cluster specific operations if applicable.
Achin Gupta85876392014-07-31 17:45:51 +0100175 */
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000176
177 /* Prevent interrupts from spuriously waking up this cpu */
178 plat_arm_gic_cpuif_disable();
179
180 /* Turn redistributor off */
181 plat_arm_gic_redistif_off();
182
183 /* Program the power controller to power off this cpu. */
184 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100185
Soby Mathewfec4eb72015-07-01 16:16:20 +0100186 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
187 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100188 fvp_cluster_pwrdwn_common();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100189
Achin Gupta4f6ad662013-10-25 09:08:21 +0100190}
191
192/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100193 * FVP handler called when a power domain is about to be suspended. The
194 * target_state encodes the power state that each level should transition to.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100195 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000196static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197{
Soby Mathewffb4ab12014-09-26 15:08:52 +0100198 unsigned long mpidr;
199
Soby Mathewfec4eb72015-07-01 16:16:20 +0100200 /*
201 * FVP has retention only at cpu level. Just return
202 * as nothing is to be done for retention.
203 */
204 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
205 ARM_LOCAL_STATE_RET)
Soby Mathew74e52a72014-10-02 16:56:51 +0100206 return;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207
Soby Mathewfec4eb72015-07-01 16:16:20 +0100208 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
209 ARM_LOCAL_STATE_OFF);
210
Soby Mathewffb4ab12014-09-26 15:08:52 +0100211 /* Get the mpidr for this cpu */
212 mpidr = read_mpidr_el1();
213
Achin Gupta85876392014-07-31 17:45:51 +0100214 /* Program the power controller to enable wakeup interrupts. */
215 fvp_pwrc_set_wen(mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100216
Jeenu Viswambharan6ad35482016-12-09 11:14:34 +0000217 /* Prevent interrupts from spuriously waking up this cpu */
218 plat_arm_gic_cpuif_disable();
219
220 /*
221 * The Redistributor is not powered off as it can potentially prevent
222 * wake up events reaching the CPUIF and/or might lead to losing
223 * register context.
224 */
225
Achin Gupta85876392014-07-31 17:45:51 +0100226 /* Perform the common cluster specific operations */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100227 if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
228 ARM_LOCAL_STATE_OFF)
Achin Gupta85876392014-07-31 17:45:51 +0100229 fvp_cluster_pwrdwn_common();
Soby Mathew9ca28062017-10-11 16:08:58 +0100230
231 /* Perform the common system specific operations */
232 if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
233 ARM_LOCAL_STATE_OFF)
234 arm_system_pwr_domain_save();
235
236 /* Program the power controller to power off this cpu. */
237 fvp_pwrc_write_ppoffr(read_mpidr_el1());
Achin Gupta4f6ad662013-10-25 09:08:21 +0100238}
239
240/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100241 * FVP handler called when a power domain has just been powered on after
242 * being turned off earlier. The target_state encodes the low power state that
243 * each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000245static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246{
Soby Mathew12012dd2015-10-26 14:01:53 +0000247 fvp_power_domain_on_finish_common(target_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100248
Achin Gupta85876392014-07-31 17:45:51 +0100249 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000250 plat_arm_gic_pcpu_init();
251
252 /* Program the gic per-cpu distributor or re-distributor interface */
253 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100254}
255
256/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +0100257 * FVP handler called when a power domain has just been powered on after
258 * having been suspended earlier. The target_state encodes the low power state
259 * that each level has woken up from.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100260 * TODO: At the moment we reuse the on finisher and reinitialize the secure
261 * context. Need to implement a separate suspend finisher.
262 ******************************************************************************/
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000263static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264{
Soby Mathewfec4eb72015-07-01 16:16:20 +0100265 /*
266 * Nothing to be done on waking up from retention from CPU level.
267 */
268 if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
269 ARM_LOCAL_STATE_RET)
270 return;
271
Soby Mathew12012dd2015-10-26 14:01:53 +0000272 fvp_power_domain_on_finish_common(target_state);
273
274 /* Enable the gic cpu interface */
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000275 plat_arm_gic_cpuif_enable();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100276}
277
Juan Castillo4dc4a472014-08-12 11:17:06 +0100278/*******************************************************************************
279 * FVP handlers to shutdown/reboot the system
280 ******************************************************************************/
281static void __dead2 fvp_system_off(void)
282{
283 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000284 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
285 V2M_CFGCTRL_START |
286 V2M_CFGCTRL_RW |
287 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100288 wfi();
289 ERROR("FVP System Off: operation not handled.\n");
290 panic();
291}
292
293static void __dead2 fvp_system_reset(void)
294{
295 /* Write the System Configuration Control Register */
Dan Handley2b6b5742015-03-19 19:17:53 +0000296 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL,
297 V2M_CFGCTRL_START |
298 V2M_CFGCTRL_RW |
299 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100300 wfi();
301 ERROR("FVP System Reset: operation not handled.\n");
302 panic();
303}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100304
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100305static int fvp_node_hw_state(u_register_t target_cpu,
306 unsigned int power_level)
307{
308 unsigned int psysr;
309 int ret;
310
311 /*
312 * The format of 'power_level' is implementation-defined, but 0 must
313 * mean a CPU. We also allow 1 to denote the cluster
314 */
315 if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1)
316 return PSCI_E_INVALID_PARAMS;
317
318 /*
319 * Read the status of the given MPDIR from FVP power controller. The
320 * power controller only gives us on/off status, so map that to expected
321 * return values of the PSCI call
322 */
323 psysr = fvp_pwrc_read_psysr(target_cpu);
324 if (psysr == PSYSR_INVALID)
325 return PSCI_E_INVALID_PARAMS;
326
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000327 if (power_level == ARM_PWR_LVL0) {
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100328 ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF;
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000329 } else {
330 /* power_level == ARM_PWR_LVL1 */
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100331 ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF;
Jeenu Viswambharan095529a2016-08-04 09:43:15 +0100332 }
333
334 return ret;
335}
336
Soby Mathew9ca28062017-10-11 16:08:58 +0100337/*
338 * The FVP doesn't truly support power management at SYSTEM power domain. The
339 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform
340 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver
341 * save and restore sequences on FVP.
342 */
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000343#if !ARM_BL31_IN_DRAM
344static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state)
Soby Mathew9ca28062017-10-11 16:08:58 +0100345{
346 unsigned int i;
347
348 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
349 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
350}
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000351#endif
Soby Mathew9ca28062017-10-11 16:08:58 +0100352
Achin Gupta4f6ad662013-10-25 09:08:21 +0100353/*******************************************************************************
Soby Mathew9ca28062017-10-11 16:08:58 +0100354 * Handler to filter PSCI requests.
355 ******************************************************************************/
356/*
357 * The system power domain suspend is only supported only via
358 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
359 * will be downgraded to the lower level.
360 */
361static int fvp_validate_power_state(unsigned int power_state,
362 psci_power_state_t *req_state)
363{
364 int rc;
365 rc = arm_validate_power_state(power_state, req_state);
366
367 /*
368 * Ensure that the system power domain level is never suspended
369 * via PSCI CPU SUSPEND API. Currently system suspend is only
370 * supported via PSCI SYSTEM SUSPEND API.
371 */
372 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN;
373 return rc;
374}
375
376/*
377 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the
378 * `fvp_validate_power_state`, we do not downgrade the system power
379 * domain level request in `power_state` as it will be used to query the
380 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
381 */
382static int fvp_translate_power_state_by_mpidr(u_register_t mpidr,
383 unsigned int power_state,
384 psci_power_state_t *output_state)
385{
386 return arm_validate_power_state(power_state, output_state);
387}
388
389/*******************************************************************************
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100390 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
391 * platform layer will take care of registering the handlers with PSCI.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100392 ******************************************************************************/
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100393plat_psci_ops_t plat_arm_psci_pm_ops = {
Soby Mathewfec4eb72015-07-01 16:16:20 +0100394 .cpu_standby = fvp_cpu_standby,
395 .pwr_domain_on = fvp_pwr_domain_on,
396 .pwr_domain_off = fvp_pwr_domain_off,
397 .pwr_domain_suspend = fvp_pwr_domain_suspend,
398 .pwr_domain_on_finish = fvp_pwr_domain_on_finish,
399 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish,
Juan Castillo4dc4a472014-08-12 11:17:06 +0100400 .system_off = fvp_system_off,
Soby Mathew74e52a72014-10-02 16:56:51 +0100401 .system_reset = fvp_system_reset,
Soby Mathew9ca28062017-10-11 16:08:58 +0100402 .validate_power_state = fvp_validate_power_state,
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100403 .validate_ns_entrypoint = arm_validate_psci_entrypoint,
Soby Mathew9ca28062017-10-11 16:08:58 +0100404 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100405 .get_node_hw_state = fvp_node_hw_state,
Antonio Nino Diaz0b6af832017-11-22 12:00:44 +0000406#if !ARM_BL31_IN_DRAM
407 /*
408 * The TrustZone Controller is set up during the warmboot sequence after
409 * resuming the CPU from a SYSTEM_SUSPEND. If BL31 is located in SRAM
410 * this is not a problem but, if it is in TZC-secured DRAM, it tries to
411 * reconfigure the same memory it is running on, causing an exception.
412 */
Soby Mathew9ca28062017-10-11 16:08:58 +0100413 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state,
Antonio Nino Diaz0b6af832017-11-22 12:00:44 +0000414#endif
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100415#if !RESET_TO_BL31 && !RESET_TO_SP_MIN
Antonio Nino Diaz0b6af832017-11-22 12:00:44 +0000416 /*
417 * mem_protect is not supported in RESET_TO_BL31 and RESET_TO_SP_MIN,
418 * as that would require mapping in all of NS DRAM into BL31 or BL32.
419 */
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100420 .mem_protect_chk = arm_psci_mem_protect_chk,
421 .read_mem_protect = arm_psci_read_mem_protect,
422 .write_mem_protect = arm_nor_psci_write_mem_protect,
423#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100424};