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git01.mediatek.com / filogic / atf / b71a9e694d38f5aab9dd541ce74e6d49a95d15f8 / . / plat / arm / board / juno / juno_common.c
blob: 9570d2d4c7d525e002390350e4e431d2a29820eb [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]1/*
Louis Mayencourt3e7c38a2019-07-31 15:03:44 +0100[diff] [blame]2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]5 */
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +0000[diff] [blame]6
7#include <platform_def.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +0000[diff] [blame]8#include <plat/arm/common/plat_arm.h>
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]9
10/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100[diff] [blame]11 * Table of memory regions for different BL stages to map using the MMU.
Roberto Vargas344ff022018-10-19 16:44:18 +0100[diff] [blame]12 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
13 * of mapping it.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]14 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]15#ifdef IMAGE_BL1
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]16const mmap_region_t plat_arm_mmap[] = {
17 ARM_MAP_SHARED_RAM,
Soby Mathew94273572018-03-07 11:32:04 +0000[diff] [blame]18 V2M_MAP_FLASH0_RW,
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]19 V2M_MAP_IOFPGA,
20 CSS_MAP_DEVICE,
21 SOC_CSS_MAP_DEVICE,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100[diff] [blame]22#if TRUSTED_BOARD_BOOT
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +0100[diff] [blame]23 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100[diff] [blame]24 ARM_MAP_NS_DRAM1,
25#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]26 {0}
27};
28#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]29#ifdef IMAGE_BL2
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]30const mmap_region_t plat_arm_mmap[] = {
31 ARM_MAP_SHARED_RAM,
Soby Mathew94273572018-03-07 11:32:04 +0000[diff] [blame]32 V2M_MAP_FLASH0_RW,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100[diff] [blame]33#ifdef PLAT_ARM_MEM_PROT_ADDR
34 ARM_V2M_MAP_MEM_PROTECT,
35#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]36 V2M_MAP_IOFPGA,
37 CSS_MAP_DEVICE,
38 SOC_CSS_MAP_DEVICE,
39 ARM_MAP_NS_DRAM1,
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700[diff] [blame]40#ifdef __aarch64__
Roberto Vargasf8fda102017-08-08 11:27:20 +0100[diff] [blame]41 ARM_MAP_DRAM2,
42#endif
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +0100[diff] [blame]43#ifdef SPD_tspd
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]44 ARM_MAP_TSP_SEC_MEM,
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +0100[diff] [blame]45#endif
Summer Qin9db8f2e2017-04-24 16:49:28 +0100[diff] [blame]46#ifdef SPD_opteed
Soby Mathew874fc9e2017-09-01 13:43:50 +0100[diff] [blame]47 ARM_MAP_OPTEE_CORE_MEM,
Summer Qin9db8f2e2017-04-24 16:49:28 +0100[diff] [blame]48 ARM_OPTEE_PAGEABLE_LOAD_MEM,
49#endif
Louis Mayencourt3e7c38a2019-07-31 15:03:44 +0100[diff] [blame]50#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
51 ARM_MAP_BL1_RW,
52#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]53 {0}
54};
55#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]56#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100[diff] [blame]57const mmap_region_t plat_arm_mmap[] = {
58 ARM_MAP_SHARED_RAM,
59 CSS_MAP_DEVICE,
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100[diff] [blame]60 CSS_MAP_SCP_BL2U,
61 V2M_MAP_IOFPGA,
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100[diff] [blame]62 SOC_CSS_MAP_DEVICE,
63 {0}
64};
65#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]66#ifdef IMAGE_BL31
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]67const mmap_region_t plat_arm_mmap[] = {
68 ARM_MAP_SHARED_RAM,
69 V2M_MAP_IOFPGA,
70 CSS_MAP_DEVICE,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100[diff] [blame]71#ifdef PLAT_ARM_MEM_PROT_ADDR
72 ARM_V2M_MAP_MEM_PROTECT,
73#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]74 SOC_CSS_MAP_DEVICE,
75 {0}
76};
77#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]78#ifdef IMAGE_BL32
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]79const mmap_region_t plat_arm_mmap[] = {
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700[diff] [blame]80#ifndef __aarch64__
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000[diff] [blame]81 ARM_MAP_SHARED_RAM,
Roberto Vargas550eb082018-01-05 16:00:05 +0000[diff] [blame]82#ifdef PLAT_ARM_MEM_PROT_ADDR
83 ARM_V2M_MAP_MEM_PROTECT,
84#endif
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000[diff] [blame]85#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]86 V2M_MAP_IOFPGA,
87 CSS_MAP_DEVICE,
88 SOC_CSS_MAP_DEVICE,
89 {0}
90};
91#endif
92
93ARM_CASSERT_MMAP