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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Roberto Vargas550eb082018-01-05 16:00:05 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#include <arm_def.h>
7#include <plat_arm.h>
8
9/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010010 * Table of memory regions for different BL stages to map using the MMU.
11 * This doesn't include Trusted SRAM as arm_setup_page_tables() already
12 * takes care of mapping it.
Dan Handley9df48042015-03-19 18:58:55 +000013 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090014#ifdef IMAGE_BL1
Dan Handley9df48042015-03-19 18:58:55 +000015const mmap_region_t plat_arm_mmap[] = {
16 ARM_MAP_SHARED_RAM,
Soby Mathew94273572018-03-07 11:32:04 +000017 V2M_MAP_FLASH0_RW,
Dan Handley9df48042015-03-19 18:58:55 +000018 V2M_MAP_IOFPGA,
19 CSS_MAP_DEVICE,
20 SOC_CSS_MAP_DEVICE,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010021#if TRUSTED_BOARD_BOOT
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010022 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010023 ARM_MAP_NS_DRAM1,
24#endif
Dan Handley9df48042015-03-19 18:58:55 +000025 {0}
26};
27#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090028#ifdef IMAGE_BL2
Dan Handley9df48042015-03-19 18:58:55 +000029const mmap_region_t plat_arm_mmap[] = {
30 ARM_MAP_SHARED_RAM,
Soby Mathew94273572018-03-07 11:32:04 +000031 V2M_MAP_FLASH0_RW,
Roberto Vargasa1c16b62017-08-03 09:16:43 +010032#ifdef PLAT_ARM_MEM_PROT_ADDR
33 ARM_V2M_MAP_MEM_PROTECT,
34#endif
Dan Handley9df48042015-03-19 18:58:55 +000035 V2M_MAP_IOFPGA,
36 CSS_MAP_DEVICE,
37 SOC_CSS_MAP_DEVICE,
38 ARM_MAP_NS_DRAM1,
Roberto Vargasf8fda102017-08-08 11:27:20 +010039#ifdef AARCH64
40 ARM_MAP_DRAM2,
41#endif
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +010042#ifdef SPD_tspd
Dan Handley9df48042015-03-19 18:58:55 +000043 ARM_MAP_TSP_SEC_MEM,
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +010044#endif
Summer Qin9db8f2e2017-04-24 16:49:28 +010045#ifdef SPD_opteed
Soby Mathew874fc9e2017-09-01 13:43:50 +010046 ARM_MAP_OPTEE_CORE_MEM,
Summer Qin9db8f2e2017-04-24 16:49:28 +010047 ARM_OPTEE_PAGEABLE_LOAD_MEM,
48#endif
Dan Handley9df48042015-03-19 18:58:55 +000049 {0}
50};
51#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090052#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +010053const mmap_region_t plat_arm_mmap[] = {
54 ARM_MAP_SHARED_RAM,
55 CSS_MAP_DEVICE,
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010056 CSS_MAP_SCP_BL2U,
57 V2M_MAP_IOFPGA,
Yatharth Kochar3a11eda2015-10-14 15:28:11 +010058 SOC_CSS_MAP_DEVICE,
59 {0}
60};
61#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090062#ifdef IMAGE_BL31
Dan Handley9df48042015-03-19 18:58:55 +000063const mmap_region_t plat_arm_mmap[] = {
64 ARM_MAP_SHARED_RAM,
65 V2M_MAP_IOFPGA,
66 CSS_MAP_DEVICE,
Roberto Vargasa1c16b62017-08-03 09:16:43 +010067#ifdef PLAT_ARM_MEM_PROT_ADDR
68 ARM_V2M_MAP_MEM_PROTECT,
69#endif
Dan Handley9df48042015-03-19 18:58:55 +000070 SOC_CSS_MAP_DEVICE,
71 {0}
72};
73#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090074#ifdef IMAGE_BL32
Dan Handley9df48042015-03-19 18:58:55 +000075const mmap_region_t plat_arm_mmap[] = {
Yatharth Kochar2694cba2016-11-14 12:00:41 +000076#ifdef AARCH32
77 ARM_MAP_SHARED_RAM,
Roberto Vargas550eb082018-01-05 16:00:05 +000078#ifdef PLAT_ARM_MEM_PROT_ADDR
79 ARM_V2M_MAP_MEM_PROTECT,
80#endif
Yatharth Kochar2694cba2016-11-14 12:00:41 +000081#endif
Dan Handley9df48042015-03-19 18:58:55 +000082 V2M_MAP_IOFPGA,
83 CSS_MAP_DEVICE,
84 SOC_CSS_MAP_DEVICE,
85 {0}
86};
87#endif
88
89ARM_CASSERT_MMAP