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git01.mediatek.com / filogic / atf / fa3cf0bf903ad0d8320713870ca58410e1ab8758 / . / plat / arm / board / common / board_css_common.c
blob: 1758a235a9ed0b6ace54a185b6b7fa39dc4e0128 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]1/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100[diff] [blame]2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame^]4 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]5 */
6#include <arm_def.h>
7#include <plat_arm.h>
8
9/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100[diff] [blame]10 * Table of memory regions for different BL stages to map using the MMU.
11 * This doesn't include Trusted SRAM as arm_setup_page_tables() already
12 * takes care of mapping it.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]13 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]14#ifdef IMAGE_BL1
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]15const mmap_region_t plat_arm_mmap[] = {
16 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +0100[diff] [blame]17 V2M_MAP_FLASH0_RO,
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]18 V2M_MAP_IOFPGA,
19 CSS_MAP_DEVICE,
20 SOC_CSS_MAP_DEVICE,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100[diff] [blame]21#if TRUSTED_BOARD_BOOT
22 ARM_MAP_NS_DRAM1,
23#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]24 {0}
25};
26#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]27#ifdef IMAGE_BL2
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]28const mmap_region_t plat_arm_mmap[] = {
29 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +0100[diff] [blame]30 V2M_MAP_FLASH0_RO,
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]31 V2M_MAP_IOFPGA,
32 CSS_MAP_DEVICE,
33 SOC_CSS_MAP_DEVICE,
34 ARM_MAP_NS_DRAM1,
35 ARM_MAP_TSP_SEC_MEM,
36 {0}
37};
38#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]39#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100[diff] [blame]40const mmap_region_t plat_arm_mmap[] = {
41 ARM_MAP_SHARED_RAM,
42 CSS_MAP_DEVICE,
43 SOC_CSS_MAP_DEVICE,
44 {0}
45};
46#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]47#ifdef IMAGE_BL31
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]48const mmap_region_t plat_arm_mmap[] = {
49 ARM_MAP_SHARED_RAM,
50 V2M_MAP_IOFPGA,
51 CSS_MAP_DEVICE,
52 SOC_CSS_MAP_DEVICE,
53 {0}
54};
55#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]56#ifdef IMAGE_BL32
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]57const mmap_region_t plat_arm_mmap[] = {
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000[diff] [blame]58#ifdef AARCH32
59 ARM_MAP_SHARED_RAM,
60#endif
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]61 V2M_MAP_IOFPGA,
62 CSS_MAP_DEVICE,
63 SOC_CSS_MAP_DEVICE,
64 {0}
65};
66#endif
67
68ARM_CASSERT_MMAP
69