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Dan Handley9df48042015-03-19 18:58:55 +00001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <arm_def.h>
31#include <plat_arm.h>
32
33/*
34 * Table of regions for different BL stages to map using the MMU.
35 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
36 * arm_configure_mmu_elx() will give the available subset of that,
37 */
38#if IMAGE_BL1
39const mmap_region_t plat_arm_mmap[] = {
40 ARM_MAP_SHARED_RAM,
41 V2M_MAP_FLASH0,
42 V2M_MAP_IOFPGA,
43 CSS_MAP_DEVICE,
44 SOC_CSS_MAP_DEVICE,
45 {0}
46};
47#endif
48#if IMAGE_BL2
49const mmap_region_t plat_arm_mmap[] = {
50 ARM_MAP_SHARED_RAM,
51 V2M_MAP_FLASH0,
52 V2M_MAP_IOFPGA,
53 CSS_MAP_DEVICE,
54 SOC_CSS_MAP_DEVICE,
55 ARM_MAP_NS_DRAM1,
56 ARM_MAP_TSP_SEC_MEM,
57 {0}
58};
59#endif
60#if IMAGE_BL31
61const mmap_region_t plat_arm_mmap[] = {
62 ARM_MAP_SHARED_RAM,
63 V2M_MAP_IOFPGA,
64 CSS_MAP_DEVICE,
65 SOC_CSS_MAP_DEVICE,
66 {0}
67};
68#endif
69#if IMAGE_BL32
70const mmap_region_t plat_arm_mmap[] = {
71 V2M_MAP_IOFPGA,
72 CSS_MAP_DEVICE,
73 SOC_CSS_MAP_DEVICE,
74 {0}
75};
76#endif
77
78ARM_CASSERT_MMAP
79