Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PLATFORM_DEF_H__ |
| 32 | #define __PLATFORM_DEF_H__ |
| 33 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 34 | #include <arm_def.h> |
| 35 | #include <board_arm_def.h> |
| 36 | #include <board_css_def.h> |
| 37 | #include <common_def.h> |
| 38 | #include <css_def.h> |
| 39 | #include <soc_css_def.h> |
| 40 | #include <tzc400.h> |
| 41 | #include <v2m_def.h> |
Sandrine Bailleux | 1fe4336 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 42 | #include "../juno_def.h" |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 43 | |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 44 | /* Required platform porting definitions */ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 45 | /* Juno supports system power domain */ |
| 46 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
| 47 | #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 48 | JUNO_CLUSTER_COUNT + \ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 49 | PLATFORM_CORE_COUNT) |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 50 | #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ |
| 51 | JUNO_CLUSTER1_CORE_COUNT) |
| 52 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 53 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 54 | * Other platform porting definitions are provided by included headers |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 55 | */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 56 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 57 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 58 | * Required ARM standard platform porting definitions |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 59 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 60 | #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 61 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 62 | /* Use the bypass address */ |
| 63 | #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 64 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 65 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 66 | * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB |
| 67 | * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of |
| 68 | * flash |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 69 | */ |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 70 | #if TRUSTED_BOARD_BOOT |
| 71 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 72 | #else |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 73 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 |
| 74 | #endif /* TRUSTED_BOARD_BOOT */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 75 | |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 76 | /* |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 77 | * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 78 | * defined for ARM development platforms. |
| 79 | */ |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 80 | #if ARM_BOARD_OPTIMISE_MEM |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 81 | /* |
| 82 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 83 | * plat_arm_mmap array defined for each BL stage. |
| 84 | */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 85 | #ifdef IMAGE_BL1 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 86 | # define PLAT_ARM_MMAP_ENTRIES 7 |
| 87 | # define MAX_XLAT_TABLES 4 |
| 88 | #endif |
| 89 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 90 | #ifdef IMAGE_BL2 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 91 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 92 | # define MAX_XLAT_TABLES 3 |
| 93 | #endif |
| 94 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 95 | #ifdef IMAGE_BL2U |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 96 | # define PLAT_ARM_MMAP_ENTRIES 4 |
| 97 | # define MAX_XLAT_TABLES 3 |
| 98 | #endif |
| 99 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 100 | #ifdef IMAGE_BL31 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 101 | # define PLAT_ARM_MMAP_ENTRIES 5 |
| 102 | # define MAX_XLAT_TABLES 2 |
| 103 | #endif |
| 104 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 105 | #ifdef IMAGE_BL32 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 106 | # define PLAT_ARM_MMAP_ENTRIES 4 |
| 107 | # define MAX_XLAT_TABLES 3 |
| 108 | #endif |
| 109 | |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 110 | /* |
| 111 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 112 | * plus a little space for growth. |
| 113 | */ |
| 114 | #if TRUSTED_BOARD_BOOT |
| 115 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 |
| 116 | #else |
| 117 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 |
| 118 | #endif |
| 119 | |
| 120 | /* |
| 121 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 122 | * little space for growth. |
| 123 | */ |
| 124 | #if TRUSTED_BOARD_BOOT |
| 125 | # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 |
| 126 | #else |
| 127 | # define PLAT_ARM_MAX_BL2_SIZE 0xC000 |
| 128 | #endif |
| 129 | |
| 130 | /* |
| 131 | * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a |
| 132 | * little space for growth. |
| 133 | */ |
| 134 | #define PLAT_ARM_MAX_BL31_SIZE 0x1D000 |
| 135 | |
| 136 | #endif /* ARM_BOARD_OPTIMISE_MEM */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 137 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 138 | /* CCI related constants */ |
| 139 | #define PLAT_ARM_CCI_BASE 0x2c090000 |
| 140 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 141 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 142 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 143 | /* System timer related constants */ |
| 144 | #define PLAT_ARM_NSTIMER_FRAME_ID 1 |
| 145 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 146 | /* TZC related constants */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 147 | #define PLAT_ARM_TZC_BASE 0x2a4a0000 |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 148 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 149 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ |
| 150 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ |
| 151 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ |
| 152 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ |
| 153 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ |
| 154 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ |
| 155 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ |
| 156 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ |
| 157 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ |
| 158 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 159 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 160 | /* |
| 161 | * Required ARM CSS based platform porting definitions |
| 162 | */ |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 163 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 164 | /* GIC related constants (no GICR in GIC-400) */ |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 165 | #define PLAT_ARM_GICD_BASE 0x2c010000 |
| 166 | #define PLAT_ARM_GICC_BASE 0x2c02f000 |
| 167 | #define PLAT_ARM_GICH_BASE 0x2c04f000 |
| 168 | #define PLAT_ARM_GICV_BASE 0x2c06f000 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 169 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 170 | /* MHU related constants */ |
| 171 | #define PLAT_CSS_MHU_BASE 0x2b1f0000 |
| 172 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 173 | /* |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 174 | * Base address of the first memory region used for communication between AP |
| 175 | * and SCP. Used by the BOM and SCPI protocols. |
| 176 | * |
| 177 | * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which |
| 178 | * means the SCP/AP configuration data gets overwritten when the AP initiates |
| 179 | * communication with the SCP. The configuration data is expected to be a |
| 180 | * 32-bit word on all CSS platforms. On Juno, part of this configuration is |
| 181 | * which CPU is the primary, according to the shift and mask definitions below. |
| 182 | */ |
| 183 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) |
| 184 | #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 |
| 185 | #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 |
| 186 | |
| 187 | /* |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 188 | * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current |
| 189 | * SCP_BL2 size plus a little space for growth. |
| 190 | */ |
| 191 | #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x1D000 |
| 192 | |
| 193 | /* |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 194 | * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current |
| 195 | * SCP_BL2U size plus a little space for growth. |
| 196 | */ |
| 197 | #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x1D000 |
| 198 | |
| 199 | /* |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 200 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 201 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 202 | * as Group 0 interrupts. |
| 203 | */ |
| 204 | #define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ |
| 205 | ARM_G1S_IRQS, \ |
Vikram Kanigiri | f3bcea2 | 2015-06-24 17:51:09 +0100 | [diff] [blame] | 206 | JUNO_IRQ_DMA_SMMU, \ |
| 207 | JUNO_IRQ_HDLCD0_SMMU, \ |
| 208 | JUNO_IRQ_HDLCD1_SMMU, \ |
| 209 | JUNO_IRQ_USB_SMMU, \ |
| 210 | JUNO_IRQ_THIN_LINKS_SMMU, \ |
| 211 | JUNO_IRQ_SEC_I2C, \ |
| 212 | JUNO_IRQ_GPU_SMMU_1, \ |
| 213 | JUNO_IRQ_ETR_SMMU |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 214 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 215 | #define PLAT_ARM_G0_IRQS ARM_G0_IRQS |
| 216 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 217 | /* |
| 218 | * Required ARM CSS SoC based platform porting definitions |
| 219 | */ |
| 220 | |
| 221 | /* CSS SoC NIC-400 Global Programmers View (GPV) */ |
| 222 | #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 223 | |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 224 | #endif /* __PLATFORM_DEF_H__ */ |