blob: 192f407c3284f305bddd24efdce0f3a727ee3b19 [file] [log] [blame]
Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
Rupinderjit Singhd2d02982022-09-12 17:25:32 +01002 * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
Usama Ariff1513622021-04-09 17:07:41 +010010 compatible = "arm,tc";
Usama Arifbec5afd2020-04-17 16:13:39 +010011 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 aliases {
16 serial0 = &soc_uart0;
17 };
18
19 chosen {
Nikos Nikoleris35800bd2021-01-21 13:50:25 +000020 stdout-path = "serial0:115200n8";
Usama Arifbec5afd2020-04-17 16:13:39 +010021 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu-map {
28 cluster0 {
29 core0 {
30 cpu = <&CPU0>;
31 };
32 core1 {
33 cpu = <&CPU1>;
34 };
35 core2 {
36 cpu = <&CPU2>;
37 };
38 core3 {
39 cpu = <&CPU3>;
40 };
Avinash Mehtaf68a0842020-10-28 16:43:28 +000041 core4 {
42 cpu = <&CPU4>;
43 };
44 core5 {
45 cpu = <&CPU5>;
46 };
47 core6 {
48 cpu = <&CPU6>;
49 };
50 core7 {
51 cpu = <&CPU7>;
52 };
Usama Arifbec5afd2020-04-17 16:13:39 +010053 };
54 };
55
Usama Arif57900782020-08-12 17:14:37 +010056 /*
57 * The timings below are just to demonstrate working cpuidle.
58 * These values may be inaccurate.
59 */
60 idle-states {
61 entry-method = "arm,psci";
62
63 CPU_SLEEP_0: cpu-sleep-0 {
64 compatible = "arm,idle-state";
65 arm,psci-suspend-param = <0x0010000>;
66 local-timer-stop;
67 entry-latency-us = <300>;
68 exit-latency-us = <1200>;
69 min-residency-us = <2000>;
70 };
71 CLUSTER_SLEEP_0: cluster-sleep-0 {
72 compatible = "arm,idle-state";
73 arm,psci-suspend-param = <0x1010000>;
74 local-timer-stop;
75 entry-latency-us = <400>;
76 exit-latency-us = <1200>;
77 min-residency-us = <2500>;
78 };
79 };
80
Chris Kayc2d29ba2021-05-18 18:49:51 +010081 amus {
82 amu: amu-0 {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 mpmm_gear0: counter@0 {
87 reg = <0>;
88
89 enable-at-el3;
90 };
91
92 mpmm_gear1: counter@1 {
93 reg = <1>;
94
95 enable-at-el3;
96 };
97
98 mpmm_gear2: counter@2 {
99 reg = <2>;
100
101 enable-at-el3;
102 };
103 };
104 };
105
Usama Arifbec5afd2020-04-17 16:13:39 +0100106 CPU0:cpu@0 {
107 device_type = "cpu";
108 compatible = "arm,armv8";
109 reg = <0x0>;
110 enable-method = "psci";
111 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100113 capacity-dmips-mhz = <406>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100114 amu = <&amu>;
115 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100116 };
117
118 CPU1:cpu@100 {
119 device_type = "cpu";
120 compatible = "arm,armv8";
121 reg = <0x100>;
122 enable-method = "psci";
123 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100124 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100125 capacity-dmips-mhz = <406>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100126 amu = <&amu>;
127 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100128 };
129
130 CPU2:cpu@200 {
131 device_type = "cpu";
132 compatible = "arm,armv8";
133 reg = <0x200>;
134 enable-method = "psci";
135 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100136 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100137 capacity-dmips-mhz = <406>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100138 amu = <&amu>;
139 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100140 };
141
142 CPU3:cpu@300 {
143 device_type = "cpu";
144 compatible = "arm,armv8";
145 reg = <0x300>;
146 enable-method = "psci";
147 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100148 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100149 capacity-dmips-mhz = <406>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100150 amu = <&amu>;
151 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100152 };
153
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000154 CPU4:cpu@400 {
155 device_type = "cpu";
156 compatible = "arm,armv8";
157 reg = <0x400>;
158 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000159 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000160 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100161 capacity-dmips-mhz = <912>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100162 amu = <&amu>;
163 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000164 };
165
166 CPU5:cpu@500 {
167 device_type = "cpu";
168 compatible = "arm,armv8";
169 reg = <0x500>;
170 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000171 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000172 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100173 capacity-dmips-mhz = <912>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100174 amu = <&amu>;
175 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000176 };
177
178 CPU6:cpu@600 {
179 device_type = "cpu";
180 compatible = "arm,armv8";
181 reg = <0x600>;
182 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000183 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000184 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100185 capacity-dmips-mhz = <912>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100186 amu = <&amu>;
187 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000188 };
189
190 CPU7:cpu@700 {
191 device_type = "cpu";
192 compatible = "arm,armv8";
193 reg = <0x700>;
194 enable-method = "psci";
Usama Arif410d50d2021-04-07 11:48:22 +0100195 clocks = <&scmi_dvfs 2>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000196 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100197 capacity-dmips-mhz = <1024>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100198 amu = <&amu>;
199 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000200 };
201
Usama Arifbec5afd2020-04-17 16:13:39 +0100202 };
203
Arunachalam Ganapathy948bb442020-12-14 12:31:32 +0000204 reserved-memory {
205 #address-cells = <2>;
206 #size-cells = <2>;
207 ranges;
208
Anders Delliena6c9b722021-12-08 21:57:21 +0000209 linux,cma {
210 compatible = "shared-dma-pool";
211 reusable;
212 size = <0x0 0x8000000>;
213 linux,cma-default;
214 };
215
Arunachalam Ganapathyac9e1202022-04-11 17:38:17 +0100216 optee@0xf8e00000 {
Davidson K4662a882022-12-14 17:38:14 +0530217 compatible = "restricted-dma-pool";
Arunachalam Ganapathyac9e1202022-04-11 17:38:17 +0100218 reg = <0x00000000 0xf8e00000 0 0x00200000>;
Arunachalam Ganapathy948bb442020-12-14 12:31:32 +0000219 };
220 };
221
Usama Arifbec5afd2020-04-17 16:13:39 +0100222 psci {
Usama Arif7a64bfa2021-05-27 20:09:17 +0100223 compatible = "arm,psci-1.0", "arm,psci-0.2";
Usama Arifbec5afd2020-04-17 16:13:39 +0100224 method = "smc";
225 };
226
227 sram: sram@6000000 {
228 compatible = "mmio-sram";
229 reg = <0x0 0x06000000 0x0 0x8000>;
230
231 #address-cells = <1>;
232 #size-cells = <1>;
233 ranges = <0 0x0 0x06000000 0x8000>;
234
235 cpu_scp_scmi_mem: scp-shmem@0 {
236 compatible = "arm,scmi-shmem";
237 reg = <0x0 0x80>;
238 };
239 };
240
241 mbox_db_rx: mhu@45010000 {
Usama Arifb315c702021-05-27 20:01:39 +0100242 compatible = "arm,mhuv2-rx","arm,primecell";
Usama Arifbec5afd2020-04-17 16:13:39 +0100243 reg = <0x0 0x45010000 0x0 0x1000>;
244 clocks = <&soc_refclk100mhz>;
245 clock-names = "apb_pclk";
Usama Arifb315c702021-05-27 20:01:39 +0100246 #mbox-cells = <2>;
Usama Arif884f40d2020-08-18 12:56:44 +0100247 interrupts = <0 317 4>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100248 interrupt-names = "mhu_rx";
249 mhu-protocol = "doorbell";
Usama Arifb315c702021-05-27 20:01:39 +0100250 arm,mhuv2-protocols = <0 1>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100251 };
252
253 mbox_db_tx: mhu@45000000 {
Usama Arifb315c702021-05-27 20:01:39 +0100254 compatible = "arm,mhuv2-tx","arm,primecell";
Usama Arifbec5afd2020-04-17 16:13:39 +0100255 reg = <0x0 0x45000000 0x0 0x1000>;
256 clocks = <&soc_refclk100mhz>;
257 clock-names = "apb_pclk";
Usama Arifb315c702021-05-27 20:01:39 +0100258 #mbox-cells = <2>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100259 interrupt-names = "mhu_tx";
260 mhu-protocol = "doorbell";
Usama Arifb315c702021-05-27 20:01:39 +0100261 arm,mhuv2-protocols = <0 1>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100262 };
263
Rupinderjit Singh8c901962022-02-22 21:50:33 +0000264 cmn-pmu {
265 compatible = "arm,ci-700";
266 reg = <0x0 0x50000000 0x0 0x10000000>;
267 interrupts = <0x0 460 0x4>;
268 };
269
Usama Arifbec5afd2020-04-17 16:13:39 +0100270 scmi {
271 compatible = "arm,scmi";
Usama Arifbec5afd2020-04-17 16:13:39 +0100272 mbox-names = "tx", "rx";
Usama Arifb315c702021-05-27 20:01:39 +0100273 mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
Usama Arifbec5afd2020-04-17 16:13:39 +0100274 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
275 #address-cells = <1>;
276 #size-cells = <0>;
277
278 scmi_dvfs: protocol@13 {
279 reg = <0x13>;
280 #clock-cells = <1>;
281 };
282
283 scmi_clk: protocol@14 {
284 reg = <0x14>;
285 #clock-cells = <1>;
286 };
287 };
288
289 gic: interrupt-controller@2c010000 {
290 compatible = "arm,gic-600", "arm,gic-v3";
291 #address-cells = <2>;
292 #interrupt-cells = <3>;
293 #size-cells = <2>;
294 ranges;
295 interrupt-controller;
296 reg = <0x0 0x30000000 0 0x10000>, /* GICD */
Usama Ariffdfd2502021-03-30 16:39:19 +0100297 <0x0 0x30080000 0 0x200000>; /* GICR */
Usama Arifbec5afd2020-04-17 16:13:39 +0100298 interrupts = <0x1 0x9 0x4>;
299 };
300
301 timer {
302 compatible = "arm,armv8-timer";
303 interrupts = <0x1 13 0x8>,
304 <0x1 14 0x8>,
305 <0x1 11 0x8>,
306 <0x1 10 0x8>;
307 };
308
309 soc_refclk100mhz: refclk100mhz {
310 compatible = "fixed-clock";
311 #clock-cells = <0>;
312 clock-frequency = <100000000>;
313 clock-output-names = "apb_pclk";
314 };
315
316 soc_refclk60mhz: refclk60mhz {
317 compatible = "fixed-clock";
318 #clock-cells = <0>;
319 clock-frequency = <60000000>;
320 clock-output-names = "iofpga_clk";
321 };
322
323 soc_uartclk: uartclk {
324 compatible = "fixed-clock";
325 #clock-cells = <0>;
326 clock-frequency = <50000000>;
327 clock-output-names = "uartclk";
328 };
329
330 soc_uart0: uart@7ff80000 {
331 compatible = "arm,pl011", "arm,primecell";
332 reg = <0x0 0x7ff80000 0x0 0x1000>;
333 interrupts = <0x0 116 0x4>;
334 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
335 clock-names = "uartclk", "apb_pclk";
336 status = "okay";
337 };
338
Jayanth Dodderi Chidanand2858cf52022-09-28 11:41:48 +0100339 rtc0: rtc@1C170000 {
340 compatible = "arm,pl031", "arm,primecell";
341 reg = <0x0 0x1C170000 0x0 0x1000>;
342 interrupts = <0x0 100 0x4>;
343 clocks = <&soc_refclk100mhz>;
344 clock-names = "apb_pclk";
345 wakeup-source;
346 };
Rupinderjit Singhd2d02982022-09-12 17:25:32 +0100347
Usama Arifbec5afd2020-04-17 16:13:39 +0100348 vencoder {
349 compatible = "drm,virtual-encoder";
350
351 port {
352 vencoder_in: endpoint {
Avinash Mehtadf71a602020-07-22 16:40:07 +0100353 remote-endpoint = <&dp_pl0_out0>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100354 };
355 };
356
357 display-timings {
358 panel-timing {
359 clock-frequency = <25175000>;
360 hactive = <640>;
361 vactive = <480>;
362 hfront-porch = <16>;
363 hback-porch = <48>;
364 hsync-len = <96>;
365 vfront-porch = <10>;
366 vback-porch = <33>;
367 vsync-len = <2>;
368 };
369 };
370
371 };
372
373 hdlcd: hdlcd@7ff60000 {
374 compatible = "arm,hdlcd";
375 reg = <0x0 0x7ff60000 0x0 0x1000>;
376 interrupts = <0x0 117 0x4>;
377 clocks = <&fake_hdlcd_clk>;
378 clock-names = "pxlclk";
Avinash Mehtadf71a602020-07-22 16:40:07 +0100379 status = "disabled";
Usama Arifbec5afd2020-04-17 16:13:39 +0100380
381 port {
382 hdlcd_out: endpoint {
383 remote-endpoint = <&vencoder_in>;
384 };
385 };
386 };
387
388 fake_hdlcd_clk: fake-hdlcd-clk {
389 compatible = "fixed-clock";
390 #clock-cells = <0>;
391 clock-frequency = <25175000>;
392 clock-output-names = "pxlclk";
393 };
394
395 ethernet@18000000 {
396 compatible = "smsc,lan91c111";
397 reg = <0x0 0x18000000 0x0 0x10000>;
398 interrupts = <0 109 4>;
399 };
400
401 kmi@1c060000 {
402 compatible = "arm,pl050", "arm,primecell";
403 reg = <0x0 0x001c060000 0x0 0x1000>;
404 interrupts = <0 197 4>;
405 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
406 clock-names = "KMIREFCLK", "apb_pclk";
407 };
408
409 kmi@1c070000 {
410 compatible = "arm,pl050", "arm,primecell";
411 reg = <0x0 0x001c070000 0x0 0x1000>;
412 interrupts = <0 103 4>;
413 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
414 clock-names = "KMIREFCLK", "apb_pclk";
415 };
416
417 bp_clock24mhz: clock24mhz {
418 compatible = "fixed-clock";
419 #clock-cells = <0>;
420 clock-frequency = <24000000>;
421 clock-output-names = "bp:clock24mhz";
422 };
423
424 virtio_block@1c130000 {
425 compatible = "virtio,mmio";
426 reg = <0x0 0x1c130000 0x0 0x200>;
427 interrupts = <0 204 4>;
428 };
429
Usama Arif1cd56dc2020-06-10 16:27:53 +0100430 sysreg: sysreg@1c010000 {
431 compatible = "arm,vexpress-sysreg";
432 reg = <0x0 0x001c010000 0x0 0x1000>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 };
436
437 fixed_3v3: v2m-3v3 {
438 compatible = "regulator-fixed";
439 regulator-name = "3V3";
440 regulator-min-microvolt = <3300000>;
441 regulator-max-microvolt = <3300000>;
442 regulator-always-on;
443 };
444
445 mmci@1c050000 {
446 compatible = "arm,pl180", "arm,primecell";
447 reg = <0x0 0x001c050000 0x0 0x1000>;
448 interrupts = <0 107 0x4>,
449 <0 108 0x4>;
450 cd-gpios = <&sysreg 0 0>;
451 wp-gpios = <&sysreg 1 0>;
452 bus-width = <8>;
453 max-frequency = <12000000>;
454 vmmc-supply = <&fixed_3v3>;
455 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
456 clock-names = "mclk", "apb_pclk";
457 };
458
Anders Dellien7a849802022-01-01 21:51:21 +0000459 gpu: gpu@2d000000 {
460 compatible = "arm,mali-midgard";
461 reg = <0x0 0x2d000000 0x0 0x200000>;
462 interrupts = <0 66 4>, <0 67 4>, <0 65 4>;
463 interrupt-names = "JOB", "MMU", "GPU";
464 clocks = <&soc_refclk100mhz>;
465 clock-names = "clk_mali";
Davidson Kce633122022-11-21 17:49:51 +0530466 iommus = <&smmu_700 0x200>;
Anders Dellien7a849802022-01-01 21:51:21 +0000467 operating-points = <
468 /* KHz uV */
469 50000 820000
470 >;
471 };
472
Davidson Kce633122022-11-21 17:49:51 +0530473 smmu_700: smmu_700@3f000000 {
Anders Delliena1914132022-01-01 21:56:25 +0000474 #iommu-cells = <1>;
475 compatible = "arm,smmu-v3";
Davidson Kce633122022-11-21 17:49:51 +0530476 reg = <0x0 0x3f000000 0x0 0x5000000>;
477 dma-coherent;
Anders Delliena1914132022-01-01 21:56:25 +0000478 };
479
Usama Arifbec5afd2020-04-17 16:13:39 +0100480 dp0: display@2cc00000 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 compatible = "arm,mali-d71";
484 reg = <0 0x2cc00000 0 0x20000>;
485 interrupts = <0 69 4>;
486 interrupt-names = "DPU";
487 clocks = <&scmi_clk 0>;
488 clock-names = "aclk";
Davidson Kce633122022-11-21 17:49:51 +0530489 iommus = <&smmu_700 0x100>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100490 pl0: pipeline@0 {
491 reg = <0>;
492 clocks = <&scmi_clk 1>;
493 clock-names = "pxclk";
494 pl_id = <0>;
495 ports {
496 #address-cells = <1>;
497 #size-cells = <0>;
498 port@0 {
499 reg = <0>;
500 dp_pl0_out0: endpoint {
501 remote-endpoint = <&vencoder_in>;
502 };
503 };
504 };
505 };
506
507 pl1: pipeline@1 {
508 reg = <1>;
509 clocks = <&scmi_clk 2>;
510 clock-names = "pxclk";
511 pl_id = <1>;
512 ports {
513 #address-cells = <1>;
514 #size-cells = <0>;
515 port@0 {
516 reg = <0>;
517 };
518 };
519 };
520 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000521
Davidson K65361052021-10-13 18:49:41 +0530522 ete0 {
523 compatible = "arm,embedded-trace-extension";
524 cpu = <&CPU0>;
525 };
526
527 ete1 {
528 compatible = "arm,embedded-trace-extension";
529 cpu = <&CPU1>;
530 };
531
532 ete2 {
533 compatible = "arm,embedded-trace-extension";
534 cpu = <&CPU2>;
535 };
536
537 ete3 {
538 compatible = "arm,embedded-trace-extension";
539 cpu = <&CPU3>;
540 };
541
542 ete4 {
543 compatible = "arm,embedded-trace-extension";
544 cpu = <&CPU4>;
545 };
546
547 ete5 {
548 compatible = "arm,embedded-trace-extension";
549 cpu = <&CPU5>;
550 };
551
552 ete6 {
553 compatible = "arm,embedded-trace-extension";
554 cpu = <&CPU6>;
555 };
556
557 ete7 {
558 compatible = "arm,embedded-trace-extension";
559 cpu = <&CPU7>;
560 };
561
562 trbe0 {
563 compatible = "arm,trace-buffer-extension";
564 interrupts = <1 2 4>;
565 };
Usama Arifbec5afd2020-04-17 16:13:39 +0100566};