blob: 631c92691a257aa2392a7190d81a0ee478442f33 [file] [log] [blame]
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07001#
Chris Kaye9272152021-09-28 15:52:14 +01002# Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Chris Kaye9272152021-09-28 15:52:14 +01007include common/fdt_wrappers.mk
8
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07009# platform configs
Varun Wadekar19ecdb92017-12-01 09:24:12 -080010ENABLE_CONSOLE_SPE := 1
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070011$(eval $(call add_define,ENABLE_CONSOLE_SPE))
12
Varun Wadekar602cf7e2018-04-03 13:10:48 -070013ENABLE_STRICT_CHECKING_MODE := 1
Steven Kao8f4f1022017-12-13 06:39:15 +080014$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
15
Varun Wadekar602cf7e2018-04-03 13:10:48 -070016USE_GPC_DMA := 1
17$(eval $(call add_define,USE_GPC_DMA))
18
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070019RESET_TO_BL31 := 1
20
21PROGRAMMABLE_RESET_ADDRESS := 1
22
23COLD_BOOT_SINGLE_CPU := 1
24
25# platform settings
26TZDRAM_BASE := 0x40000000
27$(eval $(call add_define,TZDRAM_BASE))
28
Ajay Gupta81621092017-08-01 15:53:04 -070029MAX_XLAT_TABLES := 25
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070030$(eval $(call add_define,MAX_XLAT_TABLES))
31
Steven Kao58d11942017-09-29 16:32:34 +080032MAX_MMAP_REGIONS := 30
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070033$(eval $(call add_define,MAX_MMAP_REGIONS))
34
David Pu70f65972019-03-18 15:14:49 -070035# enable RAS handling
Manish Pandey0e3379d2022-10-10 11:43:08 +010036HANDLE_EA_EL3_FIRST_NS := 1
David Pu70f65972019-03-18 15:14:49 -070037RAS_EXTENSION := 1
38
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070039# platform files
Varun Wadekar26dfb512019-01-17 16:36:23 -080040PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \
41 -I${SOC_DIR}/drivers/include
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070042
Varun Wadekar8b1068b2020-02-26 14:52:01 -080043BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
44 drivers/ti/uart/aarch64/16550_console.S \
Varun Wadekar498d5012017-11-15 15:52:01 -080045 lib/cpus/aarch64/denver.S \
Varun Wadekar0c9105e2019-06-13 15:32:11 -070046 ${TEGRA_DRIVERS}/bpmp_ipc/intf.c \
47 ${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \
48 ${TEGRA_DRIVERS}/memctrl/memctrl_v2.c \
49 ${TEGRA_DRIVERS}/smmu/smmu.c \
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070050 ${SOC_DIR}/drivers/mce/mce.c \
Steven Kao2cdb6782017-01-05 17:04:40 +080051 ${SOC_DIR}/drivers/mce/nvg.c \
52 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
Steven Kao530b2172017-06-23 16:18:58 +080053 ${SOC_DIR}/drivers/se/se.c \
Varun Wadekar00759902017-05-31 11:41:00 -070054 ${SOC_DIR}/plat_memctrl.c \
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070055 ${SOC_DIR}/plat_psci_handlers.c \
56 ${SOC_DIR}/plat_setup.c \
57 ${SOC_DIR}/plat_secondary.c \
Varun Wadekar00759902017-05-31 11:41:00 -070058 ${SOC_DIR}/plat_sip_calls.c \
Varun Wadekar362a6b22017-11-10 11:04:42 -080059 ${SOC_DIR}/plat_smmu.c \
60 ${SOC_DIR}/plat_trampoline.S
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070061
Varun Wadekar0c9105e2019-06-13 15:32:11 -070062ifeq (${USE_GPC_DMA}, 1)
63BL31_SOURCES += ${TEGRA_DRIVERS}/gpcdma/gpcdma.c
64endif
65
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070066ifeq (${ENABLE_CONSOLE_SPE},1)
Varun Wadekar0c9105e2019-06-13 15:32:11 -070067BL31_SOURCES += ${TEGRA_DRIVERS}/spe/shared_console.S
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070068endif
David Pu70f65972019-03-18 15:14:49 -070069
70# RAS sources
71ifeq (${RAS_EXTENSION},1)
72BL31_SOURCES += lib/extensions/ras/std_err_record.c \
73 lib/extensions/ras/ras_common.c \
74 ${SOC_DIR}/plat_ras.c
75endif
Varun Wadekar28d31022020-07-19 21:30:54 -070076
77# SPM dispatcher
78ifeq (${SPD},spmd)
Varun Wadekar28d31022020-07-19 21:30:54 -070079include lib/libfdt/libfdt.mk
80# sources to support spmd
81BL31_SOURCES += plat/common/plat_spmd_manifest.c \
Varun Wadekar28d31022020-07-19 21:30:54 -070082 ${LIBFDT_SRCS}
Chris Kaye9272152021-09-28 15:52:14 +010083
84BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
Varun Wadekar28d31022020-07-19 21:30:54 -070085endif