| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | # |
| 2 | # Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
| 7 | # platform configs |
| Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame^] | 8 | ENABLE_CONSOLE_SPE := 0 |
| 9 | $(eval $(call add_define,ENABLE_CONSOLE_SPE)) |
| 10 | |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 11 | ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0 |
| 12 | $(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) |
| 13 | |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 14 | RELOCATE_TO_BL31_BASE := 1 |
| 15 | $(eval $(call add_define,RELOCATE_TO_BL31_BASE)) |
| 16 | |
| 17 | ENABLE_CHIP_VERIFICATION_HARNESS := 0 |
| 18 | $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) |
| 19 | |
| Pritesh Raithatha | ef9fb1c | 2017-01-24 14:44:57 +0530 | [diff] [blame] | 20 | ENABLE_SMMU_DEVICE := 1 |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 21 | $(eval $(call add_define,ENABLE_SMMU_DEVICE)) |
| 22 | |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 23 | RESET_TO_BL31 := 1 |
| 24 | |
| 25 | PROGRAMMABLE_RESET_ADDRESS := 1 |
| 26 | |
| 27 | COLD_BOOT_SINGLE_CPU := 1 |
| 28 | |
| 29 | # platform settings |
| 30 | TZDRAM_BASE := 0x40000000 |
| 31 | $(eval $(call add_define,TZDRAM_BASE)) |
| 32 | |
| Varun Wadekar | a07d1c7 | 2017-08-23 14:59:09 -0700 | [diff] [blame] | 33 | PLATFORM_CLUSTER_COUNT := 4 |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 34 | $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) |
| 35 | |
| Varun Wadekar | a07d1c7 | 2017-08-23 14:59:09 -0700 | [diff] [blame] | 36 | PLATFORM_MAX_CPUS_PER_CLUSTER := 2 |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 37 | $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) |
| 38 | |
| Ajay Gupta | 8162109 | 2017-08-01 15:53:04 -0700 | [diff] [blame] | 39 | MAX_XLAT_TABLES := 25 |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 40 | $(eval $(call add_define,MAX_XLAT_TABLES)) |
| 41 | |
| Steven Kao | 58d1194 | 2017-09-29 16:32:34 +0800 | [diff] [blame] | 42 | MAX_MMAP_REGIONS := 30 |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 43 | $(eval $(call add_define,MAX_MMAP_REGIONS)) |
| 44 | |
| 45 | # platform files |
| 46 | PLAT_INCLUDES += -I${SOC_DIR}/drivers/include |
| 47 | |
| Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame^] | 48 | BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ |
| Varun Wadekar | 498d501 | 2017-11-15 15:52:01 -0800 | [diff] [blame] | 49 | lib/cpus/aarch64/denver.S \ |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 50 | ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ |
| 51 | ${COMMON_DIR}/drivers/smmu/smmu.c \ |
| 52 | ${SOC_DIR}/drivers/mce/mce.c \ |
| Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 53 | ${SOC_DIR}/drivers/mce/nvg.c \ |
| 54 | ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ |
| Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 55 | ${SOC_DIR}/drivers/se/se.c \ |
| Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 56 | ${SOC_DIR}/plat_memctrl.c \ |
| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 57 | ${SOC_DIR}/plat_psci_handlers.c \ |
| 58 | ${SOC_DIR}/plat_setup.c \ |
| 59 | ${SOC_DIR}/plat_secondary.c \ |
| Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 60 | ${SOC_DIR}/plat_sip_calls.c \ |
| Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 61 | ${SOC_DIR}/plat_smmu.c \ |
| 62 | ${SOC_DIR}/plat_trampoline.S |
| Varun Wadekar | 9d15f7e | 2019-08-21 14:01:31 -0700 | [diff] [blame^] | 63 | |
| 64 | ifeq (${ENABLE_CONSOLE_SPE},1) |
| 65 | BL31_SOURCES += ${COMMON_DIR}/drivers/spe/shared_console.S |
| 66 | endif |