Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | # |
| 2 | # Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
| 7 | # platform configs |
| 8 | ENABLE_AFI_DEVICE := 0 |
| 9 | $(eval $(call add_define,ENABLE_AFI_DEVICE)) |
| 10 | |
| 11 | ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0 |
| 12 | $(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) |
| 13 | |
| 14 | ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM := 1 |
| 15 | $(eval $(call add_define,ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM)) |
| 16 | |
| 17 | RELOCATE_TO_BL31_BASE := 1 |
| 18 | $(eval $(call add_define,RELOCATE_TO_BL31_BASE)) |
| 19 | |
| 20 | ENABLE_CHIP_VERIFICATION_HARNESS := 0 |
| 21 | $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) |
| 22 | |
Pritesh Raithatha | ef9fb1c | 2017-01-24 14:44:57 +0530 | [diff] [blame] | 23 | ENABLE_SMMU_DEVICE := 1 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 24 | $(eval $(call add_define,ENABLE_SMMU_DEVICE)) |
| 25 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 26 | RESET_TO_BL31 := 1 |
| 27 | |
| 28 | PROGRAMMABLE_RESET_ADDRESS := 1 |
| 29 | |
| 30 | COLD_BOOT_SINGLE_CPU := 1 |
| 31 | |
| 32 | # platform settings |
| 33 | TZDRAM_BASE := 0x40000000 |
| 34 | $(eval $(call add_define,TZDRAM_BASE)) |
| 35 | |
Varun Wadekar | a07d1c7 | 2017-08-23 14:59:09 -0700 | [diff] [blame] | 36 | PLATFORM_CLUSTER_COUNT := 4 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 37 | $(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) |
| 38 | |
Varun Wadekar | a07d1c7 | 2017-08-23 14:59:09 -0700 | [diff] [blame] | 39 | PLATFORM_MAX_CPUS_PER_CLUSTER := 2 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 40 | $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) |
| 41 | |
Ajay Gupta | 8162109 | 2017-08-01 15:53:04 -0700 | [diff] [blame] | 42 | MAX_XLAT_TABLES := 25 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 43 | $(eval $(call add_define,MAX_XLAT_TABLES)) |
| 44 | |
Steven Kao | 58d1194 | 2017-09-29 16:32:34 +0800 | [diff] [blame^] | 45 | MAX_MMAP_REGIONS := 30 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 46 | $(eval $(call add_define,MAX_MMAP_REGIONS)) |
| 47 | |
| 48 | # platform files |
| 49 | PLAT_INCLUDES += -I${SOC_DIR}/drivers/include |
| 50 | |
| 51 | BL31_SOURCES += lib/cpus/aarch64/denver.S \ |
| 52 | ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ |
| 53 | ${COMMON_DIR}/drivers/smmu/smmu.c \ |
| 54 | ${SOC_DIR}/drivers/mce/mce.c \ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 55 | ${SOC_DIR}/drivers/mce/nvg.c \ |
| 56 | ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 57 | ${SOC_DIR}/plat_memctrl.c \ |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 58 | ${SOC_DIR}/plat_psci_handlers.c \ |
| 59 | ${SOC_DIR}/plat_setup.c \ |
| 60 | ${SOC_DIR}/plat_secondary.c \ |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 61 | ${SOC_DIR}/plat_sip_calls.c \ |
| 62 | ${SOC_DIR}/plat_smmu.c |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 63 | |
| 64 | ifeq (${ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM}, 1) |
| 65 | BL31_SOURCES += ${SOC_DIR}/plat_trampoline.S |
| 66 | endif |