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git01.mediatek.com / filogic / atf / 0c9105ec3ddff2e94fc9bf748621d89784dbf82d / . / plat / nvidia / tegra / soc / t194 / platform_t194.mk
blob: 7573ed23be9a35f6d4257945e12674682cbd8e9e [file] [log] [blame]
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]1#
Varun Wadekare9d69f72017-11-29 15:34:58 -0800[diff] [blame]2# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# platform configs
Varun Wadekar19ecdb92017-12-01 09:24:12 -0800[diff] [blame]8ENABLE_CONSOLE_SPE := 1
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]9$(eval $(call add_define,ENABLE_CONSOLE_SPE))
10
Varun Wadekar602cf7e2018-04-03 13:10:48 -0700[diff] [blame]11ENABLE_STRICT_CHECKING_MODE := 1
Steven Kao8f4f1022017-12-13 06:39:15 +0800[diff] [blame]12$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
13
Varun Wadekar602cf7e2018-04-03 13:10:48 -0700[diff] [blame]14USE_GPC_DMA := 1
15$(eval $(call add_define,USE_GPC_DMA))
16
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]17RESET_TO_BL31 := 1
18
19PROGRAMMABLE_RESET_ADDRESS := 1
20
21COLD_BOOT_SINGLE_CPU := 1
22
23# platform settings
24TZDRAM_BASE := 0x40000000
25$(eval $(call add_define,TZDRAM_BASE))
26
Ajay Gupta81621092017-08-01 15:53:04 -0700[diff] [blame]27MAX_XLAT_TABLES := 25
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]28$(eval $(call add_define,MAX_XLAT_TABLES))
29
Steven Kao58d11942017-09-29 16:32:34 +0800[diff] [blame]30MAX_MMAP_REGIONS := 30
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]31$(eval $(call add_define,MAX_MMAP_REGIONS))
32
David Pu70f65972019-03-18 15:14:49 -0700[diff] [blame]33# enable RAS handling
34HANDLE_EA_EL3_FIRST := 1
35RAS_EXTENSION := 1
36
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]37# platform files
Varun Wadekar26dfb512019-01-17 16:36:23 -0800[diff] [blame]38PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \
39 -I${SOC_DIR}/drivers/include
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]40
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]41BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
Varun Wadekar498d5012017-11-15 15:52:01 -0800[diff] [blame]42 lib/cpus/aarch64/denver.S \
Varun Wadekar0c9105e2019-06-13 15:32:11 -0700[diff] [blame^]43 ${TEGRA_DRIVERS}/bpmp_ipc/intf.c \
44 ${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \
45 ${TEGRA_DRIVERS}/memctrl/memctrl_v2.c \
46 ${TEGRA_DRIVERS}/smmu/smmu.c \
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]47 ${SOC_DIR}/drivers/mce/mce.c \
Steven Kao2cdb6782017-01-05 17:04:40 +0800[diff] [blame]48 ${SOC_DIR}/drivers/mce/nvg.c \
49 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
Steven Kao530b2172017-06-23 16:18:58 +0800[diff] [blame]50 ${SOC_DIR}/drivers/se/se.c \
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]51 ${SOC_DIR}/plat_memctrl.c \
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]52 ${SOC_DIR}/plat_psci_handlers.c \
53 ${SOC_DIR}/plat_setup.c \
54 ${SOC_DIR}/plat_secondary.c \
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]55 ${SOC_DIR}/plat_sip_calls.c \
Varun Wadekar362a6b22017-11-10 11:04:42 -0800[diff] [blame]56 ${SOC_DIR}/plat_smmu.c \
57 ${SOC_DIR}/plat_trampoline.S
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]58
Varun Wadekar0c9105e2019-06-13 15:32:11 -0700[diff] [blame^]59ifeq (${USE_GPC_DMA}, 1)
60BL31_SOURCES += ${TEGRA_DRIVERS}/gpcdma/gpcdma.c
61endif
62
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]63ifeq (${ENABLE_CONSOLE_SPE},1)
Varun Wadekar0c9105e2019-06-13 15:32:11 -0700[diff] [blame^]64BL31_SOURCES += ${TEGRA_DRIVERS}/spe/shared_console.S
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]65endif
David Pu70f65972019-03-18 15:14:49 -0700[diff] [blame]66
67# RAS sources
68ifeq (${RAS_EXTENSION},1)
69BL31_SOURCES += lib/extensions/ras/std_err_record.c \
70 lib/extensions/ras/ras_common.c \
71 ${SOC_DIR}/plat_ras.c
72endif