Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
Mikael Olsson | 0232da2 | 2021-02-12 17:30:16 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <drivers/arm/tzc400.h> |
| 11 | #if TRUSTED_BOARD_BOOT |
| 12 | #include <drivers/auth/mbedtls/mbedtls_config.h> |
| 13 | #endif |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 14 | #include <plat/arm/board/common/board_css_def.h> |
| 15 | #include <plat/arm/board/common/v2m_def.h> |
| 16 | #include <plat/arm/common/arm_def.h> |
| 17 | #include <plat/arm/css/common/css_def.h> |
| 18 | #include <plat/arm/soc/common/soc_css_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 19 | #include <plat/common/common_def.h> |
| 20 | |
Sandrine Bailleux | 1fe4336 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 21 | #include "../juno_def.h" |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 22 | |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 23 | /* Required platform porting definitions */ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 24 | /* Juno supports system power domain */ |
| 25 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
| 26 | #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 27 | JUNO_CLUSTER_COUNT + \ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 28 | PLATFORM_CORE_COUNT) |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 29 | #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ |
| 30 | JUNO_CLUSTER1_CORE_COUNT) |
| 31 | |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 32 | /* Cryptocell HW Base address */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 33 | #define PLAT_CRYPTOCELL_BASE UL(0x60050000) |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 34 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 35 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 36 | * Other platform porting definitions are provided by included headers |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 37 | */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 38 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 39 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 40 | * Required ARM standard platform porting definitions |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 41 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 42 | #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 43 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 44 | #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 45 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 46 | /* Use the bypass address */ |
Sathees Balya | 6f07a60 | 2018-11-02 14:56:06 +0000 | [diff] [blame] | 47 | #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ |
| 48 | BL1_ROM_BYPASS_OFFSET) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 49 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 50 | #define NSRAM_BASE UL(0x2e000000) |
| 51 | #define NSRAM_SIZE UL(0x00008000) /* 32KB */ |
Chris Kay | 42fbdfc | 2018-05-10 14:27:45 +0100 | [diff] [blame] | 52 | |
Suyash Pathak | 00b9983 | 2020-02-12 10:36:20 +0530 | [diff] [blame] | 53 | #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) |
| 54 | #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) |
| 55 | |
Zelalem Aweke | cb6b562 | 2021-07-26 21:28:42 -0500 | [diff] [blame] | 56 | /* Range of kernel DTB load address */ |
| 57 | #define JUNO_DTB_DRAM_MAP_START ULL(0x82000000) |
| 58 | #define JUNO_DTB_DRAM_MAP_SIZE ULL(0x00008000) /* 32KB */ |
Mikael Olsson | 0232da2 | 2021-02-12 17:30:16 +0100 | [diff] [blame] | 59 | |
| 60 | #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ |
Zelalem Aweke | cb6b562 | 2021-07-26 21:28:42 -0500 | [diff] [blame] | 61 | JUNO_DTB_DRAM_MAP_START, \ |
| 62 | JUNO_DTB_DRAM_MAP_SIZE, \ |
Mikael Olsson | 0232da2 | 2021-02-12 17:30:16 +0100 | [diff] [blame] | 63 | MT_MEMORY | MT_RO | MT_NS) |
| 64 | |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 65 | /* virtual address used by dynamic mem_protect for chunk_base */ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 66 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 67 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 68 | /* |
Sathees Balya | 6f07a60 | 2018-11-02 14:56:06 +0000 | [diff] [blame] | 69 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 70 | */ |
| 71 | |
| 72 | #if USE_ROMLIB |
| 73 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) |
| 74 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 75 | #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) |
Sathees Balya | 6f07a60 | 2018-11-02 14:56:06 +0000 | [diff] [blame] | 76 | #else |
| 77 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) |
| 78 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 79 | #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) |
Sathees Balya | 6f07a60 | 2018-11-02 14:56:06 +0000 | [diff] [blame] | 80 | #endif |
| 81 | |
| 82 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 83 | * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB |
| 84 | * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of |
| 85 | * flash |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 86 | */ |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 87 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 88 | #if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 89 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 90 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 91 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 92 | #endif /* TRUSTED_BOARD_BOOT */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 93 | |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 94 | /* |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 95 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 96 | * plat_arm_mmap array defined for each BL stage. |
| 97 | */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 98 | #ifdef IMAGE_BL1 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 99 | # define PLAT_ARM_MMAP_ENTRIES 7 |
| 100 | # define MAX_XLAT_TABLES 4 |
| 101 | #endif |
| 102 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 103 | #ifdef IMAGE_BL2 |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 104 | #ifdef SPD_opteed |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 105 | # define PLAT_ARM_MMAP_ENTRIES 11 |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 106 | # define MAX_XLAT_TABLES 5 |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 107 | #else |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 108 | # define PLAT_ARM_MMAP_ENTRIES 10 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 109 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 110 | #endif |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 111 | #endif |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 112 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 113 | #ifdef IMAGE_BL2U |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 114 | # define PLAT_ARM_MMAP_ENTRIES 5 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 115 | # define MAX_XLAT_TABLES 3 |
| 116 | #endif |
| 117 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 118 | #ifdef IMAGE_BL31 |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 119 | # define PLAT_ARM_MMAP_ENTRIES 7 |
Mikael Olsson | 0232da2 | 2021-02-12 17:30:16 +0100 | [diff] [blame] | 120 | # define MAX_XLAT_TABLES 5 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 121 | #endif |
| 122 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 123 | #ifdef IMAGE_BL32 |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 124 | # define PLAT_ARM_MMAP_ENTRIES 6 |
Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 125 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 126 | #endif |
| 127 | |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 128 | /* |
| 129 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 130 | * plus a little space for growth. |
| 131 | */ |
| 132 | #if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 133 | # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 134 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 135 | # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 136 | #endif |
| 137 | |
| 138 | /* |
| 139 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 140 | * little space for growth. |
| 141 | */ |
| 142 | #if TRUSTED_BOARD_BOOT |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 143 | #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 144 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION) |
Amit Daniel Kachhap | 4a8c7f9 | 2018-03-23 11:56:23 +0530 | [diff] [blame] | 145 | #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 146 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 147 | #else |
Louis Mayencourt | 438aa72 | 2019-10-11 14:31:13 +0100 | [diff] [blame] | 148 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 149 | #endif |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 150 | #else |
Manish V Badarkhe | fbf1fd2 | 2020-06-09 11:31:17 +0100 | [diff] [blame] | 151 | # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 152 | #endif |
| 153 | |
| 154 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 155 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 156 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 157 | * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. |
| 158 | * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 159 | */ |
Manish V Badarkhe | fbf1fd2 | 2020-06-09 11:31:17 +0100 | [diff] [blame] | 160 | #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 161 | |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 162 | #if JUNO_AARCH32_EL3_RUNTIME |
| 163 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 164 | * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is |
| 165 | * calculated using the current BL32 PROGBITS debug size plus the sizes of |
| 166 | * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. |
| 167 | * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 168 | */ |
Manish V Badarkhe | fbf1fd2 | 2020-06-09 11:31:17 +0100 | [diff] [blame] | 169 | #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 170 | #endif |
| 171 | |
Soby Mathew | 39f9c16 | 2017-08-22 14:06:19 +0100 | [diff] [blame] | 172 | /* |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 173 | * Size of cacheable stacks |
| 174 | */ |
| 175 | #if defined(IMAGE_BL1) |
| 176 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 177 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 178 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 179 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 180 | # endif |
| 181 | #elif defined(IMAGE_BL2) |
| 182 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 183 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 184 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 185 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 186 | # endif |
| 187 | #elif defined(IMAGE_BL2U) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 188 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 189 | #elif defined(IMAGE_BL31) |
| 190 | # if PLAT_XLAT_TABLES_DYNAMIC |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 191 | # define PLATFORM_STACK_SIZE UL(0x800) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 192 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 193 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 194 | # endif |
| 195 | #elif defined(IMAGE_BL32) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 196 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 197 | #endif |
| 198 | |
| 199 | /* |
Soby Mathew | 39f9c16 | 2017-08-22 14:06:19 +0100 | [diff] [blame] | 200 | * Since free SRAM space is scant, enable the ASSERTION message size |
| 201 | * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). |
| 202 | */ |
| 203 | #define PLAT_LOG_LEVEL_ASSERT 40 |
| 204 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 205 | /* CCI related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 206 | #define PLAT_ARM_CCI_BASE UL(0x2c090000) |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 207 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 208 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 209 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 210 | /* System timer related constants */ |
Antonio Nino Diaz | 6971f00 | 2018-11-06 13:14:21 +0000 | [diff] [blame] | 211 | #define PLAT_ARM_NSTIMER_FRAME_ID U(1) |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 212 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 213 | /* TZC related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 214 | #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 215 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 216 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ |
| 217 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ |
| 218 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ |
| 219 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ |
| 220 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ |
| 221 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ |
| 222 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ |
| 223 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ |
| 224 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ |
| 225 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 226 | |
Suyash Pathak | 81a5d03 | 2020-02-06 11:51:54 +0530 | [diff] [blame] | 227 | /* TZC related constants */ |
| 228 | #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL |
| 229 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 230 | /* |
| 231 | * Required ARM CSS based platform porting definitions |
| 232 | */ |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 233 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 234 | /* GIC related constants (no GICR in GIC-400) */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 235 | #define PLAT_ARM_GICD_BASE UL(0x2c010000) |
| 236 | #define PLAT_ARM_GICC_BASE UL(0x2c02f000) |
| 237 | #define PLAT_ARM_GICH_BASE UL(0x2c04f000) |
| 238 | #define PLAT_ARM_GICV_BASE UL(0x2c06f000) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 239 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 240 | /* MHU related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 241 | #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 242 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 243 | /* |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 244 | * Base address of the first memory region used for communication between AP |
| 245 | * and SCP. Used by the BOM and SCPI protocols. |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 246 | */ |
| 247 | #if !CSS_USE_SCMI_SDS_DRIVER |
| 248 | /* |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 249 | * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which |
| 250 | * means the SCP/AP configuration data gets overwritten when the AP initiates |
| 251 | * communication with the SCP. The configuration data is expected to be a |
| 252 | * 32-bit word on all CSS platforms. On Juno, part of this configuration is |
| 253 | * which CPU is the primary, according to the shift and mask definitions below. |
| 254 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 255 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 256 | #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 |
| 257 | #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 258 | #endif |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 259 | |
| 260 | /* |
Chris Kay | f8fa465 | 2020-03-12 13:50:26 +0000 | [diff] [blame] | 261 | * SCP_BL2 uses up whatever remaining space is available as it is loaded before |
| 262 | * anything else in this memory region and is handed over to the SCP before |
| 263 | * BL31 is loaded over the top. |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 264 | */ |
Chris Kay | 8ab69c8 | 2020-04-17 10:36:34 +0100 | [diff] [blame] | 265 | #define PLAT_CSS_MAX_SCP_BL2_SIZE \ |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 266 | ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) |
Chris Kay | 8ab69c8 | 2020-04-17 10:36:34 +0100 | [diff] [blame] | 267 | |
Chris Kay | f8fa465 | 2020-03-12 13:50:26 +0000 | [diff] [blame] | 268 | #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 269 | |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 270 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 271 | CSS_G1S_IRQ_PROPS(grp), \ |
| 272 | ARM_G1S_IRQ_PROPS(grp), \ |
| 273 | INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 274 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 275 | INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 276 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 277 | INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 278 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 279 | INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 280 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 281 | INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 282 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 283 | INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 284 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 285 | INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 286 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 287 | INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 288 | (grp), GIC_INTR_CFG_LEVEL) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 289 | |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 290 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 291 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 292 | /* |
| 293 | * Required ARM CSS SoC based platform porting definitions |
| 294 | */ |
| 295 | |
| 296 | /* CSS SoC NIC-400 Global Programmers View (GPV) */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 297 | #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 298 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 299 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS |
| 300 | #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS |
| 301 | |
Chandni Cherukuri | 0fdcbc0 | 2018-10-16 15:19:54 +0530 | [diff] [blame] | 302 | /* System power domain level */ |
| 303 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 |
| 304 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 305 | /* |
| 306 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 307 | */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 308 | #ifdef __aarch64__ |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 309 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 310 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
| 311 | #else |
| 312 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 313 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 314 | #endif |
| 315 | |
Aditya Angadi | 7f8837b | 2019-12-31 14:23:53 +0530 | [diff] [blame] | 316 | /* Number of SCMI channels on the platform */ |
| 317 | #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) |
| 318 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 319 | #endif /* PLATFORM_DEF_H */ |