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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaze40306b2017-01-13 15:03:07 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7#ifndef __ARCH_HELPERS_H__
8#define __ARCH_HELPERS_H__
9
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010010#include <arch.h> /* for additional register definitions */
11#include <cdefs.h> /* For __dead2 */
12#include <stdint.h>
Antonio Nino Diaze40306b2017-01-13 15:03:07 +000013#include <sys/types.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010014
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010015/**********************************************************************
16 * Macros which create inline functions to read or write CPU system
17 * registers
18 *********************************************************************/
19
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000020#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
Masahiro Yamada6292d772018-02-02 21:19:17 +090021static inline u_register_t read_ ## _name(void) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000022{ \
Masahiro Yamada6292d772018-02-02 21:19:17 +090023 u_register_t v; \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000024 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
25 return v; \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010026}
27
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000028#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
Masahiro Yamada6292d772018-02-02 21:19:17 +090029static inline void write_ ## _name(u_register_t v) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000030{ \
31 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010032}
33
Roberto Vargasc51cdb72017-09-18 09:53:25 +010034#define SYSREG_WRITE_CONST(reg_name, v) \
35 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010036
37/* Define read function for system register */
38#define DEFINE_SYSREG_READ_FUNC(_name) \
39 _DEFINE_SYSREG_READ_FUNC(_name, _name)
40
41/* Define read & write function for system register */
42#define DEFINE_SYSREG_RW_FUNCS(_name) \
43 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
44 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
45
46/* Define read & write function for renamed system register */
47#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
48 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
49 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
50
Achin Gupta92712a52015-09-03 14:18:02 +010051/* Define read function for renamed system register */
52#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
53 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
54
55/* Define write function for renamed system register */
56#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
57 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
58
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010059/**********************************************************************
60 * Macros to create inline functions for system instructions
61 *********************************************************************/
62
63/* Define function for simple system instruction */
64#define DEFINE_SYSOP_FUNC(_op) \
Juan Castillo2d552402014-06-13 17:05:10 +010065static inline void _op(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010066{ \
67 __asm__ (#_op); \
68}
69
70/* Define function for system instruction with type specifier */
71#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
Juan Castillo2d552402014-06-13 17:05:10 +010072static inline void _op ## _type(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010073{ \
74 __asm__ (#_op " " #_type); \
75}
76
77/* Define function for system instruction with register parameter */
78#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
79static inline void _op ## _type(uint64_t v) \
80{ \
81 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
82}
Achin Gupta4f6ad662013-10-25 09:08:21 +010083
84/*******************************************************************************
85 * TLB maintenance accessor prototypes
86 ******************************************************************************/
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +000087
88#if ERRATA_A57_813419
89/*
90 * Define function for TLBI instruction with type specifier that implements
91 * the workaround for errata 813419 of Cortex-A57.
92 */
93#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\
94static inline void tlbi ## _type(void) \
95{ \
96 __asm__("tlbi " #_type "\n" \
97 "dsb ish\n" \
98 "tlbi " #_type); \
99}
100
101/*
102 * Define function for TLBI instruction with register parameter that implements
103 * the workaround for errata 813419 of Cortex-A57.
104 */
105#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \
106static inline void tlbi ## _type(uint64_t v) \
107{ \
108 __asm__("tlbi " #_type ", %0\n" \
109 "dsb ish\n" \
110 "tlbi " #_type ", %0" : : "r" (v)); \
111}
112#endif /* ERRATA_A57_813419 */
113
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100114DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
115DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
116DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
117DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000118#if ERRATA_A57_813419
119DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3)
120DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is)
121#else
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100122DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
123DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000124#endif
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100125DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100126
Antonio Nino Diazac998032017-02-27 17:23:54 +0000127DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
128DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
129DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
130DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000131#if ERRATA_A57_813419
132DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is)
133DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is)
134#else
Antonio Nino Diazac998032017-02-27 17:23:54 +0000135DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
136DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000137#endif
Antonio Nino Diazac998032017-02-27 17:23:54 +0000138
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139/*******************************************************************************
140 * Cache maintenance accessor prototypes
141 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100142DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
143DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
144DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
145DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
146DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
147DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
148DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
149DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
150
Varun Wadekar97625e32015-03-13 14:59:03 +0530151/*******************************************************************************
152 * Address translation accessor prototypes
153 ******************************************************************************/
154DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
155DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
156DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
157DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100158DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
Varun Wadekar97625e32015-03-13 14:59:03 +0530159
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000160void flush_dcache_range(uintptr_t addr, size_t size);
161void clean_dcache_range(uintptr_t addr, size_t size);
162void inv_dcache_range(uintptr_t addr, size_t size);
163
164void dcsw_op_louis(u_register_t op_type);
165void dcsw_op_all(u_register_t op_type);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100166
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100167void disable_mmu_el1(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100168void disable_mmu_el3(void);
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100169void disable_mmu_icache_el1(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100170void disable_mmu_icache_el3(void);
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100171
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172/*******************************************************************************
173 * Misc. accessor prototypes
174 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100175
Roberto Vargasc51cdb72017-09-18 09:53:25 +0100176#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
177#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100178
Varun Wadekar97625e32015-03-13 14:59:03 +0530179DEFINE_SYSREG_READ_FUNC(par_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100180DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
181DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
dp-armee3457b2017-05-23 09:32:49 +0100182DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100183DEFINE_SYSREG_READ_FUNC(CurrentEl)
184DEFINE_SYSREG_RW_FUNCS(daif)
185DEFINE_SYSREG_RW_FUNCS(spsr_el1)
186DEFINE_SYSREG_RW_FUNCS(spsr_el2)
187DEFINE_SYSREG_RW_FUNCS(spsr_el3)
188DEFINE_SYSREG_RW_FUNCS(elr_el1)
189DEFINE_SYSREG_RW_FUNCS(elr_el2)
190DEFINE_SYSREG_RW_FUNCS(elr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100192DEFINE_SYSOP_FUNC(wfi)
193DEFINE_SYSOP_FUNC(wfe)
194DEFINE_SYSOP_FUNC(sev)
195DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
Soby Mathewed995662014-12-30 16:11:42 +0000196DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Juan Castillo2e86cb12016-01-13 15:01:09 +0000197DEFINE_SYSOP_TYPE_FUNC(dmb, st)
198DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Soby Mathewed995662014-12-30 16:11:42 +0000199DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100200DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000201DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Soby Mathewed995662014-12-30 16:11:42 +0000202DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100203DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100204DEFINE_SYSOP_FUNC(isb)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100205
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100206uint32_t get_afflvl_shift(uint32_t);
207uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100210void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
211 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
212void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
213 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100214
215/*******************************************************************************
216 * System register accessor prototypes
217 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100218DEFINE_SYSREG_READ_FUNC(midr_el1)
219DEFINE_SYSREG_READ_FUNC(mpidr_el1)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000220DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100221
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100222DEFINE_SYSREG_RW_FUNCS(scr_el3)
223DEFINE_SYSREG_RW_FUNCS(hcr_el2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100225DEFINE_SYSREG_RW_FUNCS(vbar_el1)
226DEFINE_SYSREG_RW_FUNCS(vbar_el2)
227DEFINE_SYSREG_RW_FUNCS(vbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100228
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100229DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
230DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
231DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100233DEFINE_SYSREG_RW_FUNCS(actlr_el1)
234DEFINE_SYSREG_RW_FUNCS(actlr_el2)
235DEFINE_SYSREG_RW_FUNCS(actlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100237DEFINE_SYSREG_RW_FUNCS(esr_el1)
238DEFINE_SYSREG_RW_FUNCS(esr_el2)
239DEFINE_SYSREG_RW_FUNCS(esr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100240
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100241DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
242DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
243DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100245DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
246DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
247DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100248
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100249DEFINE_SYSREG_RW_FUNCS(far_el1)
250DEFINE_SYSREG_RW_FUNCS(far_el2)
251DEFINE_SYSREG_RW_FUNCS(far_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100252
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100253DEFINE_SYSREG_RW_FUNCS(mair_el1)
254DEFINE_SYSREG_RW_FUNCS(mair_el2)
255DEFINE_SYSREG_RW_FUNCS(mair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100256
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100257DEFINE_SYSREG_RW_FUNCS(amair_el1)
258DEFINE_SYSREG_RW_FUNCS(amair_el2)
259DEFINE_SYSREG_RW_FUNCS(amair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100260
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100261DEFINE_SYSREG_READ_FUNC(rvbar_el1)
262DEFINE_SYSREG_READ_FUNC(rvbar_el2)
263DEFINE_SYSREG_READ_FUNC(rvbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100265DEFINE_SYSREG_RW_FUNCS(rmr_el1)
266DEFINE_SYSREG_RW_FUNCS(rmr_el2)
267DEFINE_SYSREG_RW_FUNCS(rmr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100268
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100269DEFINE_SYSREG_RW_FUNCS(tcr_el1)
270DEFINE_SYSREG_RW_FUNCS(tcr_el2)
271DEFINE_SYSREG_RW_FUNCS(tcr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100272
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100273DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
274DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
275DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100276
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100277DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000279DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
280
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100281DEFINE_SYSREG_RW_FUNCS(cptr_el2)
282DEFINE_SYSREG_RW_FUNCS(cptr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100283
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100284DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
285DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
286DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
287DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
288DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
289DEFINE_SYSREG_READ_FUNC(cntpct_el0)
290DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100291
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100292DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100293
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100294DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
295
Andrew Thoelke4e126072014-06-04 21:10:52 +0100296DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
297DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
developer550bf5e2016-07-11 16:05:23 +0800298DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100299
Soby Mathew26fb90e2015-01-06 21:36:55 +0000300DEFINE_SYSREG_READ_FUNC(isr_el1)
301
Dan Handley0cdebbd2015-03-30 17:15:16 +0100302DEFINE_SYSREG_READ_FUNC(ctr_el0)
303
David Cunado5f55e282016-10-31 17:37:34 +0000304DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100305DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
David Cunadoc14b08e2016-11-25 00:21:59 +0000306DEFINE_SYSREG_RW_FUNCS(hstr_el2)
307DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
David Cunado4168f2f2017-10-02 17:41:39 +0100308DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
David Cunado5f55e282016-10-31 17:37:34 +0000309
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100310DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
311DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
312DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
313DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100314DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100315DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
316DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
317DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
318DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
319DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
320DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
321DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
322DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100323DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100324
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000325DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100326DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
327DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
328DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
329DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
330
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100331DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100332
David Cunadoce88eee2017-10-20 11:30:57 +0100333DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
334DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
335
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100336#define IS_IN_EL(x) \
337 (GET_EL(read_CurrentEl()) == MODE_EL##x)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100338
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100339#define IS_IN_EL1() IS_IN_EL(1)
340#define IS_IN_EL3() IS_IN_EL(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100341
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000342/*
343 * Check if an EL is implemented from AA64PFR0 register fields. 'el' argument
344 * must be one of 1, 2 or 3.
345 */
346#define EL_IMPLEMENTED(el) \
347 ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL##el##_SHIFT) \
348 & ID_AA64PFR0_ELX_MASK)
349
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100350/* Previously defined accesor functions with incomplete register names */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100351
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100352#define read_current_el() read_CurrentEl()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100353
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100354#define dsb() dsbsy()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100355
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100356#define read_midr() read_midr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100357
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100358#define read_mpidr() read_mpidr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100359
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100360#define read_scr() read_scr_el3()
361#define write_scr(_v) write_scr_el3(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100362
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100363#define read_hcr() read_hcr_el2()
364#define write_hcr(_v) write_hcr_el2(_v)
Sandrine Bailleux25232af2014-05-09 11:23:11 +0100365
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100366#define read_cpacr() read_cpacr_el1()
367#define write_cpacr(_v) write_cpacr_el1(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100368
Achin Gupta4f6ad662013-10-25 09:08:21 +0100369#endif /* __ARCH_HELPERS_H__ */